112G Ethernet PHY in TSMC (N7, N5, N3P)

The Synopsys 112G Ethernet PHY IP, an integral part of Synopsys’ high-speed SerDes IP portfolio, meets the growing high bandwidth and low latency needs of high-performance data center applications. Using leading-edge design, analysis, simulation, and measurement techniques, the 112G Ethernet PHY delivers exceptional signal integrity and jitter performance that exceeds the IEEE 802.3ck and OIF standards electrical specifications. The PHY is small
in area, high in performance demonstrating zero BER in greater than 45dB channels, and powerefficient at less than 5pJ/bit.
The PHY supports the Pulse-Amplitude Modulation 4-Level (PAM-4) and NonReturn-to-Zero (NRZ) signaling to deliver up to 800G Ethernet. The configurable transmitter and DSP-based receiver with analog-to-digital converter (ADC) enable designers to control and optimize signal integrity and performance. The CCA algorithm provides a robust performance across voltage and temperature variations. The low jitter PLLs and multi-loop
clock and data recovery circuits provide robust timing recovery and better jitter performance, while the embedded bit error rate (BER) tester and non-
destructive 2D eye monitor provide on-chip testability and visibility into channel performance. The PHY integrates with the Synopsys Physical Coding Sublayer and Digital Controllers/Media Access Controller (MAC) IP solutions to reduce design time and to help designers achieve first-pass silicon success.
Combined with Synopsys’ routing feasibility study, packages substrate guidelines, signal and power integrity models, and thorough crosstalk analysis, Synopsys provides a comprehensive 112G Ethernet PHY solution for fast and reliable SoC integration

• Optimized for performance, power, and area
• Includes one, two, or four full-duplex PAM-4 transceivers (transmit and receive functions)
• Supports IEEE and OIF standards: IEEE 802.3ck, CEI-112G
• Includes auto-negotiation and link training capabilities – IEEE 802.3 clause 73
• Low jitter transmitter and receiver (dual loop clock and data recovery) clock architectures
• Multi-lane PHY shares a single clock and support core
• Supports both internal and external reference clock connections to the PHY
• Configurable transmitter and DSP-based receiver with analog-to-digital converter
• Optimal receiver jitter tolerance supports a wider range of board layout designs, immunity to interference (cross talk), and reduces design constraints on board signal paths
• Contains embedded pseudo random bit sequence (PRBS) for internal and external loopbacks
• Embedded bit error rate (BER) tester and non-destructive internal eye monitor

• Supports full-duplex 1.25 to 112Gbps data rates in 1, 2, and 4 lanes
• Enables 100G, 200G, 400G, 800G
• Ethernet interconnects for wired network infrastructure
• Supports IEEE 802.3ck and OIF standards electrical specifications
• Meets the performance requirements of chip-to-chip, chip-to-module, and backplane interconnects
• DAC-based PAM-4 transmitter includes feed forward equalization (FFE)
• Digital-based receiver consists of analog front-end (AFE), ADC, and digital signal processor (DSP)
• High-performance receive equalization supports channel loss of 45dB
• Continuous calibration and adaptation (CCA) provides robust performance across voltage, and temperature
• Low jitter phase-locked loops (PLLs) provide robust timing recovery and better jitter performance

• Hyperscale data center
• Enterprise and campus networks
• HIgh-performance computing/networking
• Service provider networks
• Artificial intelligence and machine learning

• Verilog models and test bench; Protocol-specific test bench; Liberty timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl); GDSII; IP-XACT XML files with register details; ATPG models; IBIS-AMI models; Documentation