Die-to-Die, High Bandwidth Interconnect PHY in TSMC (N7, N5)

The Synopsys High-Bandwidth Interconnect PHY IP enables high bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. Implementing a wide-parallel and clock-forwarded PHY interface, the IP targets advanced 2.5D packaging to take advantage of much finer pitch die-to-die connections in interposer-based technologies, such as TSMC® Chip-on-Wafer-on-Substrate (CoWoS), than traditional flip-chip organic substrates. The Synopsys High-Bandwidth Interconnect PHY delivers data rates up to 4Gbps per pin in a flexible architecture that includes up to 80 receive and 80 transmit connections per channel and up to 24 channels per PHY with one redundant lane per channel to improve production yield. The Synopsys High-Bandwidth Interconnect PHY IP is compliant with IEEE 1149.1 (JTAG) and 1149.6 (AC JTAG) boundary scan. The built-in self-test (BIST), internal loopback, and external PHY-to-PHY link tests provide on-chip testability and visibility into channel performance. The Synopsys High-Bandwidth Interconnect PHY IP with Synopsys’ USR/XSR PHY IP, supporting 16 lanes with a data rate of up to 112Gbps per lane using NRZ and PAM-4 signaling, provide a comprehensive die-to-die IP portfolio that is suitable for all packaging technologies.