UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data centers, AI, and networking applications. The PHY’s flexible architecture supports standard and advanced package technologies and delivers up to 4Tbps bandwidth in a multi-module configuration. Supporting widely used protocols such as PCI Express and CXL and enabling latency-optimized NoC-to-NoC links with streaming protocols, the IP offers maximum performance, minimum latency and implementation flexibility.

Synopsys UCIe PHY IP delivers high energy- efficiency with an optimized architecture that uses clock forwarding and low-voltage signaling. The IP implements a comprehensive set of testability features to ensure known good dies and offers test and repair capabilities to improve package assembly yield. Robust die-to-die link operation is ensured with embedded training and calibration algorithms.

Synopsys UCIe PHY IP interoperates with Synopsys UCIe Controller IP to deliver a complete, low-latency solution for die-to-die links in any package.

• Data rates up to 16Gbps per pin
• Self-contained hard macro
• Self-calibrating and training
• Side band channel for initialization and parameter exchange
• Built-in self-test (BIST), internal loopback, and external PHY-to-PHY link test
• Flexible configuration: 64 RX and TX pins per module (advanced package) or 16 RX and TX pins per module (standard package)
• Built-in test and repair functionality with redundant pins to maximize yield
• NS (north, south) orientation, EW (east, west) possible

• Delivers up to 4Tbps with up to 5.2Tbps/ mm of die edge
• High-bandwidth, low-power, low-latency multi-module PHY for applications requiring reliable connections between dies within a package; Partitioning a large SoC into multiple smaller SoCs for flexibility in configuration or for improving yield; Packaging multiple SoCs to create complex subsystems; Connecting a SoC to smaller dies containing multiple lanes of SerDes or other functions to implement the SoC in a different process node or foundry than that of the smaller dies
• Supports advanced packaging technologies such as silicon interposer, silicon bridge or RDL fanout
• Supports standard packaging technologies such as organic substrate or laminate

• Multi-Die SoC for: High-performance computing and servers; Artificial intelligence / machine learning; Networking and infrastructure; Consumer and mobile

• Verilog models and test bench
• Protocol-specific test bench
• Liberty™ timing views (.lib), LEF abstracts (.lef), CDL netlist (.cdl)
• GDSII
• IP-XACT XML files with register details
• ATPG models
• IBIS-AMI models
• Documentation