The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips. It provides standard AXI interface for the ease of integration in SoC design.
- Controller
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
The NFC IP is a NAND Flash Controller for accessing user data from NAND Flash chips. It provides standard AXI interface for the ease of integration in SoC design.
TTEEnd System A664 Core IP is a RTCA DO-254 DAL A certifiable solution which can be used in integrated modular avionics systems.
IP platform for intelligence gathering chips at the Edge
Designed to be the solution for an AI compute device right at the Edge, Sondrel’s new SFA 100 IP reference platform makes creatin…
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
Display Stream Compression (DSC) standard was announced by Video Electronics Standards Association (VESA) in 2014 for video data …
USB 3.0/ PCIe 3.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 14SF+
The combo PHY consist of Peripheral Component Interconnect Express (PCIe) compliant with PCIe 3.0 Base Specification with support…
The SiFive Performance™ P500 application processor features a thirteen-stage, triple-issue, out-of-order pipeline compatible with…
DVB-S2/S/T2/T/C Combo Demodulator IP (Silicon Proven)
The is a single-chip DVB-T, T2, C, S and S2 demodulator IP core extratced from production chip and silicon proven IP core.
GbE (10/100 Base-T) PHY IP, Silicon Proven UMC 40LP
An IEEE 802.3u compliant single-port Ethernet physical layer transceiver with low power consumption for 10BASE-Te and 100BASE-TX …
SM4 (former name “SMS4”) is a cryptographic standard published by the Office of State Commercial Cryptography Administration (OSC…
SM3 is a hash algorithm initially published by the Office of State Commercial Cryptography Administration (OSCCA) of SCA in 2010,…
CYB-AES implements Rijndael cipher encoding and decoding in compliance with the NIST Encryption Standard.
DDR4/ LPDDR4/ DDR3L PHY IP - 1866Mbps (Silicon Proven in TSMC 28HPC+)
The LPDDR4/ DDR4/ DDR3L Combo PHY IP offers low latency and supports throughput of up to 1866Mbps.
Display Port v1.4 Tx PHY & Controller IP, Silicon Proven in TSMC 40LP
Data rates for the DisplayPort transmitter PHY version 1.4 range from 1.62Gbps (RBR) to 5.4Gbps (HBR2).
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
Single-core video codec - AV1, HEVC, AVC, VP9 (VP9: Decoder only)
USB 3.1 Gen1/Gen2 PHY IP, Silicon Proven in TSMC 28HPC+
This PHY IP supports both USB 3.1 Gen1 & Gen2.
XIP7131C is a compact 1 Intellectual Property (IP) core for TLS 1.3 client-side functionality.
World-class, industry-leading, highly scalable, silicon- and PHY-agnostic IP core with 116 Gbps line rate, interoperability tested with leading Serdes providers
PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
With compatibility for PIPE 4.4 interface protocol, this Peripheral Component Interconnect Express (PCIe) x4 PHY complies with PC…
DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
The DDR4/ DDR3L/ LPDDR4 Combo PHY IP provides low latency and enables up to 3200Mbps throughput.