USB 3.0 High/Full/Low-Speed Host + Device Controller IP
USB 3.0 Dual Mode Controller IP Core uses a high performance DMA engine based on the xHCI specification and presenting either an …
DSI-2 TX/RX IP supports both transmit and receive functions in line with the DSI-2 v1.1 and D-PHY v2.0 standards.
Advanced 2D Graphics Controller
BADGE works as a graphics engine in embedded systems, but doesn’t suffer from the short life cycles affecting the usual graphics …
PCIe Testbench from Rambus emulates a Root Complex device enabling simulation of a PCI Express design.
I2C Master / Slave Controller with FIFO (AXI & AXI-Lite Bus)
The I2C is a two-wire, bi-directional serial bus, which provides a simple and efficient method of short distance data transmissio…
MIPI DSI TX Controller Subsystem
The Xilinx MIPI DSI (Display serial interface) Transmitter Subsystem implements the Mobile Industry Processor Interface (MIPI) ba…
Important Notice: The VIPP package and its cores are in maintenance mode and not recommended for new designs.
The USB4 IP solution is based on the USB4 specification from the USB Implementer Forum (USB-IF).
32 Bit - Embedded RISC-V Processor Core
The L31(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
Compact RISC-V Processor - 32 bit, 3-stage pipeline, 32 registers
The L30(F) is a small, efficient 32-bit embedded RISC-V processor aimed at embedded systems with more modest processing requireme…
Fully Self-contained Single/Multi Port USB Type-C Power Delivery IP
SiliConch SCPD3013IP is a self-contained configurable Multiport USB Type-C Power Delivery (PD) Design IP that is based on the lat…
HDMI - Ensures seamless video and audio transmission with HDMI standards
HDMI Verification IP validates HDMI controller functionality in SoC designs, ensuring compliance with HDMI standards like 1.4, 2.…
CPRI is a high-speed serial interface for network radio equipment controllers (REC) to receive and provide data to remote Radio E…
ARINC 818 Direct Memory Access (DMA) IP Core
ARINC 818 is a point-to-point serial protocol primarily used in avionics applications and supports the transmission of video, aud…
LVDS / sub-LVDS / DPHY TX - TSMC 6FFC
The LVDS/Sub-LVDS/DPHY Combo TX converts parallel RGB data and 7/8/10 bits of CMOS parallel data into serial data streams.
The Fast sort IP core is a AXI-compatible digital hardware block with internal data sorting algorithm.
The VPC-4 is a video rotator for converting landscape rasters to portrait format and for converting portrait rasters to landscape…
Standard Definition Video (PAL/NTSC) De-Interlacer, Basic Algorithm
The xc-SDDIB is a low-cost deinterlacing IP core that converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 pr…
Standard Definition Video (PAL/NTSC) De-Interlacer, Advanced Algorithm
The xc-SDDIA core converts a standard 4:2:2 formatted interlaced video stream into a 4:2:0 progressive format, which can be used …
Perspective Transformation and Lens Correction Image Processor
The logiVIEW Perspective Transformation and Lens Correction Image Processor IP core for video and imaging applications using sing…