Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit micropr…
- SPI / QSPI XSPI
- now
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Enhanced Multiprotocol Serial Communication Controller
The DEMSCC – Dual channel Multiprotocol Enhanced Serial Communication Controller, is designed for use with 8- and 16- bit micropr…
Enhanced Serial Peripheral Interface – Target IP with single, dual, and quad eSPI Bus support for Intel CPU’s
Single-core video codec - HEVC, AVC
Single-core video codec - HEVC, AVC
The Bluetooth Low Energy (BLE) technology supports the BLE standard defined by the International Standards Organization SIG, incl…
V-by-One/LVDS Rx IP, Silicon Proven in SMIC 40LL
V-by-One® HS technology targets a high-speed data transmission of video signals based on internal connection of equipment.
V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
The V-by-One® HS technology aims to transmit video signals at a high data rate using internal equipment connections.
12.5G Multiprotocol Serdes IP, Silicon Proven in SMIC 12SF++
The multi-protocol SerDes PHY includes Peripheral Component Interconnect Express (PCIe) conforming with PCIe 2.0 Base Specificati…
ARINC 818 Direct Memory Access (DMA) IP Core
ARINC 818 is a point-to-point serial protocol primarily used in avionics applications and supports the transmission of video, aud…
PCIe 3.0 Serdes PHY IP, Silicon Proven in SMIC 12SF+/SF++
This Peripheral Component Interconnect Express (PCIe) x4 PHY is compliant with PCIe 3.0 Base Specification with support of PIPE 4…
USB 3.1 Type-C PHY IP, Silicon Proven in TSMC 55ULP
USB3.1Type-C PHY IP is a high performance high speed SERDES IP designed for chips that perform high bandwidth data communication …
USB 3.1 Type-C PHY IP, Silicon Proven in SMIC 14SF+
The USB3.1Type-C PHY is a high-performance, high-speed SERDES IP designed for semiconductors that support low-power, high-bandwid…
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in UMC 55SP/EF
The combination PHY consists of a Serial ATA (SATA) conforming with the SATA 3.0 Specification, a Peripheral Component Interconne…
USB 3.0/ PCIe 2.0/ SATA 3.0 Combo PHY IP, Silicon Proven in SMIC 28SF
The combined PHY complies with USB (USB 3.0, USB 2.0), PCIe (Peripheral Component Interconnect Express), Serial ATA (SATA 3.0 Spe…
USB 2.0 PHY IP, Silicon Proven in TSMC 22ULP
The USB 2.0 PHY IP Core is a full physical layer (PHY) IP solution created for excellent performance and low power consumption.
Available The Path Margin Monitor (PMM) solution consists of multiple PMM units, a PMM controller, and associated software & EDA …
14-bit, 4.32Gsps Ultra high speed Wideband, Time-Interleaved Pipeline ADC IP
This ultra high speed wide-band Analog-to-Digital Converter is based on 16 Time Interleaved Pipeline sub-ADC followed by a digita…
DisplayPort 1.4 FEC Transmitter (Tx) ASIL-B
The DisplayPort Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specifi…
"Image Signal Processor" with the minimum functions required for image processing system
Because our ISP-IP is equipped with the minimum necessary functions, it reduces the load on the CPU that performs some solutions …
JESD204B Tx-Rx PHY IP, Silicon Proven in UMC 55SP
With the JESD204B Tx-Rx PHY IP interface, which fully supports the JESD204B synchronous serial interface, the JESD204B version sp…
JESD204B Tx-Rx PHY IP, Silicon Proven in SMIC 12SF++
In order to provide full support for the JESD204B synchronous serial interface, the JESD204B Tx-Rx PHY IP interface is compliant …