10 Gigabit Ethernet MAC IP Core
The 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between…
- Ethernet
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
10 Gigabit Ethernet MAC IP Core
The 10 Gigabit Ethernet (XGMAC) IP core is compliant with the Ethernet IEEE 802.3-2008 standard and provides an interface between…
SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
The SD 3.0/SDIO 3.0/eMMC 5.1 Host IP is a integrated host controller IP solution that supports three key memory card I/O technolo…
The eMMC5.1 PHY is a fully compliant PHY layer for JEDEC eMMC5.1 and eMMC5.1 JESD84-B50 specification.
SD 4.1 eMMC 5.1 Dual Host Controller IP
The SD 4.1/SDIO 4.0/eMMC 5.0 Host IP from Arasan Chip Systems is a integrated host controller IP solution that supports three key…
eMMC 5.1 Nex Bus Driver is a production-ready software stack for eMMC 5.1 Host Controller IP that is used to connect eMMC devices.
eMMC 5.1 is the latest specification defined by JEDEC and is designed to meet the requirements for the next level of high-perform…
This Universal NOR Flash IP supports a variety of NOR Devices and multiple Protocols, combines ease of use with high reliability,…
Embrace the future of digital media with the VESA VDC-M v1.2 Encoder IP core.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
The MIPI Alliance was created to define and promote open standards for interfaces to mobile application processors.
MIPI M-PHY® 4.1 Analog Transceiver
MIPI M-PHY Specification Version 4.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
Host / device LIN controller IP
The LIN Controllers IP– Local Interconnect Network Controllers IPs are compliant to LIN 2.0, 2.1 & 2.2A Specifications.
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…
Arasan Chip Systems is a System on Chip (SoC) Intellectual Property (IP) provider of a suite of Mobile Industry Processor Interfa…
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
VESA introduced the first Display Stream Compression (DSC) standard in 2014.
scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface ORAN IP core is a scalable and…
E-Series GPU IP delivers fast and flexible parallel compute that scales from wearables to the cloud.
DeepMentor has developed an AI IP that combines low-power and high-performance features with the RISC-V SOC.