Vendor: Arasan Chip Systems Inc. Category: SD / eMMC Controller

SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP

The SD 3.0/SDIO 3.0/eMMC 5.1 Host IP is a integrated host controller IP solution that supports three key memory card I/O technolo…

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Overview

The SD 3.0/SDIO 3.0/eMMC 5.1 Host IP is a highly integrated host controller IP solution that supports three key memory card I/O technologies:

  • SD 3.0
  • SDIO 3.0
  • eMMC 5.1

The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 3.0 / eMMC5.1 Host IP.

 

eMMC 5.1 is backward compatible to the previous versions.

Key features

eMMC 5.1 features

  • Compliant with eMMC Specification Version 5.1
  • AMBA AXI Specification Version 3.00 (Standard)
  • AMBA AHB Specification Version 2.00 (Optional)
  • OCP specification Version 2.2 (Optional)
  • Host clock rate variable between 0 and 200 MHz
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface
  • Supports eMMC5.1 Security Protocol Commands
  • Supports 32-bit and 64-bit system bus
  • Configurable FIFO size to support different block sizes
  • Supports Interrupts and wake up functionality
  • Supports Internal Clock divider for various card operational modes
  • HS400 high speed interface timing mode of up to 400 MB/s data rate
  • Field firmware update
  • eMMC device health report
  • eMMC production state awareness
  • Secure removal types
  • Backward compatible to 1-bit, 4-bit and 8-bit modes
  • Supports Primary & alternate boot modes
  • Supports Packed commands, Data Tags, Discard & Sanitize features
  • Supports 4KB block support
  • Supports Tuning for HS200 mode
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Password protection of Cards

SD Host Controller Spec v3.0* (SDXC)

  • SDIO Spec v3.0
  • SD Memory Spec v3.01
  • eSD Memory Spec v2.1

Block Diagram

SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP block diagram

Benefits

  • RTL design in Verilog
  • UHS-I PHY GDSII
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documentation

What’s Included?

  • RTL design in Verilog
  • UHS-I PHY GDSII
  • Easy-to-use test environment
  • Synthesis scripts
  • Technical documentation

Specifications

Identity

Part Number
SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP
Vendor
Arasan Chip Systems Inc.
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Arasan Chip Systems Inc.

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Frequently asked questions about SD / eMMC Controller IP cores

What is SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP?

SD 3.0 / SDIO 3.0 / eMMC 5.1 Host Controller IP is a SD / eMMC Controller IP core from Arasan Chip Systems Inc. listed on Semi IP Hub.

How should engineers evaluate this SD / eMMC Controller?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SD / eMMC Controller IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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