eMMC 5.1 is the latest specification defined by JEDEC and is designed to meet the requirements for the next level of high-performance data transfer for mobile electronic products. With its low-pin count, higher bandwidth, multiple boot mechanisms, and content security features, the eMMC 5.1 Device provides an easy migration path and greatly simplifies system design for new products, and is backward compatible with previous versions.
The eMMC 5.1 Device Controller IP is compliant with the latest eMMC specification. The controller provides a bandwidth of up to 3.2 Gb/s (400MB/s) in HS400 DDR mode running with a 200 MHz clock. A NAND Flash controller can be connected to the eMMC controller. In such an implementation, the controller’s AHB interface provides a channel for data transfers between the eMMC device controller and a NAND flash controller (also available from Arasan).
The eMMC 5.1 Device IP supports all new features including high-performance HS400 DDR mode, field firmware update, production state, post-production data integrity, device health, and others. The eMMC device IP is backward compatible with previous versions of eMMC, including HS200, MMC 1-bit, 4-bit, and 8-bit modes.
eMMC 5.1 Device IP simplifies system design by supporting power-on booting without the upper level of the software driver. The eMMC controller shields the host system from the functional differences among various NAND flash architectures (such as MLC). The explicit sleep mode allows the host system to instruct the eMMC 5.0 device controller to directly enter a low power sleep mode. The controller supports block lengths or sector sizes of 512, 1024, 2048, and 4096 bytes.
