Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers.
- MIPI RFFE
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Mobile radio communication is trending towards complex multi-radio systems comprising several transceivers.
Mobile radio communication systems are complex multi-radio systems comprising several transceivers.
MIPI M-PHY® 3.1 Analog Transceiver
MIPI M-PHY Specification Version 3.1 is a low pin count, power efficient, inter-chip serial interface with high bandwidth capabil…
The MIPI® D-PHY is compliant to the MIPI D-PHY Specification v2.1.
MIPI D-PHY Analog Transceiver IP Core
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI®) Alliance was created to d…
Combination MIPI CPHY-DPHY Analog Interface
The MIPI C-PHY V1.2 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
MIPI CPHY v1.1 Analog Interface
The MIPI CPHY V1.1 improves throughput over a bandwidth-limited channel, allowing more data without an increased signaling clock.
The LLI Controller connects two chips together to create a single “virtual chip”, with both chips sharing the same memory.
To address the explosive growth in the mobile industry, the Mobile Industry Processor Interface (MIPI) Alliance was created to de…
The High Speed Synchronous Serial Interface (HSI) Controller is used to provide high bandwidth, point-to-point, serial communicat…
The DSI Tx Controller IP is designed to provide MIPI DSI 1.3 – compliant high-speed serial connectivity for the host (mobile appl…
The DSI v1.3 Receiver Controller IP is designed to provide MIPI DSI 1.3 compliant high-speed serial connectivity for device (mobi…
MIPI DSI-2 Transmitter Controller IP Core
The MIPI Display Serial Interface (DSI-2) Transmitter (host processor interface) Controller IP provides a high-speed serial inter…
MIPI DSI-2 Receiver IP Controller Core
The MIPI Display Serial Interface (DSI-2) Receiver (display panel interface) Controller IP provides a high-speed serial interface…
Arasan Chip Systems is a SOC IP provider of a suite of MIPI compliant IP solutions, which consist of IP cores, verification IP, s…
The silicon-proven Gigabit Ethernet IP core provides a 10/100 Mbps Media Independent Interface (MII) and a 1000 Mbps Gigabit Medi…
Fast Ethernet Media Access Controller
The Fast Ethernet Media Access Controller (FEMAC) with AHB or AXI Interface core incorporates the essential protocol requirements…
The 10/100 Ethernet Media Access Controller (MAC) IP core is compliant with the Ethernet IEEE 802.3-2002 standard and has passed …
The 802.3 Ethernet Device Driver is developed to support both the 10/ 100 Ethernet IP as well as its Gigabit Ethernet IP.
Gigabit Ethernet with IEEE 1588 and AVB
The Gigabit Ethernet Media Access Controller IP is compliant with the Ethernet IEEE 802.3-2008 standard and supports protocol ext…