MIPI D-PHY v2.1 IP Core

The MIPI® D-PHY is compliant to the MIPI D-PHY Specification v2.1.

This specification is primarily intended to define a solution for a bit-data rate range of:

• 80 to 1500 Mbps per Lane without de-skew calibration
• up to 2500 Mbps with de-skew calibration,
• up to 4500 Mbps with equalization.

When the DUT implementation supports a data rate greater than 1500 Mbps, it shall also support de-skew capability. When a PHY implementation supports a data rate more than 2500 Mbps, it shall also support equalization, and Spread Spectrum Clocking shall be available.

Arasan D-PHY IP Core is seamlessly integrated with Arasan’s MIPI CSI IP and DSI IP Controller Cores.

Arasan offers industry’s broadest portfolio of foundry and process technology support for MIPI D-PHY. The MIPI D-PHY IP is available in foundry processes spanning 7nm to 180nm. Arasan specializes in porting Analog Transceiver IP Cores to new foundry processes.

Arasan’s MIPI® D-PHY IP Core is fully compliant to the D-PHY specification version 2.1. It provides a point to point connection between master and slave or host and device that comply with a relevant MIPI®

• Compliant to MIPI® Alliance Standard for D-PHY specification Version 2.1
• Supports D-PHY 1.1 synchronous transfer mode at high speed mode with a bit rate of 80-1500 Mb/s without deskew calibration
• Supports DPHY 1.2 for 1500 – 2500 Mb/s with deskew calibration.
• Supports DPHY 2.1 for 2500 – 4500 Mb/s with deskew calibration.
• Asynchronous transfer at low power mode with a bit rate of 10 Mb/s
• Spaced one hot encoding for Low power [LP] data
• One clock lane and four data lanes
• On-chip clock generation configurable for either transmitter or a receiver
• Clock lane supports unidirectional communication
• On-chip clock generation configurable for either receiver
• Data lanes support transfer of data in high speed mode.
• Features include ultralow power mode, high speed mode and control mode.
• Has clock divider unit to generate clock for parallel data transmission from and to the PPI
• Supports standard PHY receiver and PPI interface compliant to MIPI Specification
• Testability for Analog Rx with DLL and DFE.
• Supports High speed mode in Forward communication and for Stuck-At Scan for Digital Testing
• Runs off 0.8V+/-10%, 1.2V+/-10%, 1.8V +/- 10% supply
• Has inbuilt calibration to calibrate RX impedance. Also, can manipulate those impedance manually through trim registers
• Supports polarity swap

• Silicon proven, fully compliant core
• Extensive Quality Methodology
• Premier direct support from Arasan IP core designers
• Easy-to-use industry standard test environment
• Available in various foundry processes
• No external (off-chip) components required
• Can be ported to other processes

• GDS-II Database
• LVS Netlist
• Physical Abstract Models (LEF)
• Timing Models (LIB)
• Process Specific Integration Guide
• Technical Documentation