Accelerated confidence in simulation-based verification of RTL designs with NVMe interfaces over PCIe or Fabric links The Avery N…
- Verification IP
Semiconductor IP cores (Intellectual Property cores) are reusable design blocks used in SoC and ASIC development to accelerate time-to-market and reduce design complexity.
These IP cores span a broad range of technologies, including Analog & Mixed Signal, Compute Acceleration, Graphics & Vision, Interface Connectivity , Memory Interfaces, Security, Wireless, System Peripheral, Embedded Memories, and Foundation Libraries. The catalog covers everything from analog front-ends, data converters, processors, DSPs, AI accelerators, and imaging solutions to high-speed connectivity, memory controllers and PHYs, cryptographic engines, embedded memory macros, standard cell libraries, and wireless communication IP.
This catalog allows you to explore and compare IP cores from leading vendors, based on performance, power, process node compatibility, and application domain.
Whether you are designing for automotive, wireless communication, consumer electronics, or data centers, you can find the right IP solutions for your system requirements.
Accelerated confidence in simulation-based verification of RTL designs with NVMe interfaces over PCIe or Fabric links The Avery N…
The FFT4T core implements a 128 point complex FFT and IFFT over 12 data streams in hardware.
APB Post-Quantum Cryptography Accelerator IP Core
Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards.
IGAHBMZ03A is a High Bandwidth Memory 4 Physical Layer (HBM4 PHY) that is compliant with JEDEC HBM4 DRAM Specification JESD270-4.
The Multi-Channel AXI DMA engine IP Core for AXI4 is a programmable AXI Stream to AXI memory mapped bridge with sophisticated dat…
Neuromorphic Processor IP (Second Generation)
Akida is a neural processor platform inspired by the cognitive ability and efficiency of the human brain.
USB 2.0 Mass Storage Devices Design Platform
The USB 2.0 Mass Storage Design Platform is a , integrated solution, dedicated to a wide range of USB-based Mass Storage Devices.
The K-best decoder is part of the MIMO decoder.
Wi-Fi 7(be) RF Transceiver IP in TSMC 22nm
The Wi-Fi 7 (802.11be) RF transceiver IP, operating in 2.4GHz / 5GHz / 6GHz bands, is tailored for next-generation high-performan…
Ku-Band Phased Array Tx-FE in TSMC 180nm RF
The TRV801TSM180RF IP is a Ku-Band (14GHz to 14.5GHz) Transmitter (Tx) in TSMC 180nm RF CMOS process technology.
Ku-Band Phased Array Rx-FE in TSMC 180nm RF
The TRV501TSM180RF IP is a Ku-Band (10.7GHz to 12.75GHz) Receiver (Rx) RFFE TSMC 180nm RF CMOS process technology.
The Superspeed Inter-chip Controller (USB 3.0 SSIC Adapter) uses the MIPI-M-PHY (Type-1) v.
USB 3.0 Device Upgrade IP Core
The USB 3.0 Device Upgrade IP enables designers in the PC, mobile, consumer and communication markets to bring significant power …
The USB 3.0 Device IP core enables designers in the PC, mobile, consumer and communication markets to bring significant power and…
The USB 2.0 PHY IP core is a transceiver compliant with the USB 2.0 Transceiver Macrocell Interface Plus (UTMI+) level 3 specific…
The USB 2.0 OTG IP Core is compliant with the OTG Supplement Rev.
The USB 2.0 Hub IP core is a USB 2.0 specification compliant hub core that supports 480 Mbit/s in High Speed (HS) mode, 12 Mbit/s…
The USB 2.0 Host IP is a USB 2.0 specification compliant host IP core with an optional AHB, PCI, or custom host interface.
The USB 2.0 Device IP core is Arasan’s latest development that enables designers in the PC, mobile, consumer and communication ma…
High Speed Inter-CHIP USB 2.0 PHY
USB is the ubiquitous peripherals interconnect of choice for a large number of computing and consumer applications.