APB Post-Quantum Cryptography Accelerator IP Core

Implements ML-KEM and ML-DSA post-quantum cryptography digital signature standards. The system interface is an microprocessor slave bus (APB, AHB, AXI options are available).

The design is fully synchronous and requires only minimal CPU intervention due to internal microprogramming sequencer.

The core contains three accelerators:

• The number theoretic transform NTT accelerator also capable of other vector polynomial operations
• The FIPS-202 accelerator supporting SHA-3, SHAKE128 and SHAKE256 algorithms
• The packing/unpacking accelerator that handles the key and signature formats defined by FIPS-203 and FIPS-204

True random number generator (needed for key generation or randomization of signing) is not included. The true random generator IP core TRNG1 can be used for that purpose.

Performance

• Support for ML-KEM(FIPS-203, Kyber) and ML-DSA algorithms(FIPS-204, Dilithium) with built-in NTT and SHAKE128/SHAKE256/SHA-3 engines accessible externally
• Self-contained, except for the single-port external RAM banks
• Uses 32-bit-wide APB Lite interface
• Supports all MS-DSA algorithms defined in FIPS-204 (from Category 2 ML-DSA-44, Category 3 ML-DSA-65, Category 5 ML-DSA-87) and all FIPS-203 ML-KEM algorithms (ML-KEM-512, ML-KEM-768, and ML-KEM- 1024).
• An SDK is provided for software development with support for ML-DSA (key generation, signing, and signature verification) and ML-KEM (key generation, key encapsulation, and key decapsulation).
• High clock rate. Timing closure at 1 GHz clock in ASIC with easy, higher frequencies are possible.
• Deliverables include Verilog test bench and test vectors

• Post-Quantum cryptgraphy

• Synthesizable Verilog RTL source code
• Test bench (self-checking)
• Test vectors
• Expected results
• Software Development Kit (SDK)
• User Documentation