Learn more about Interrupt Controller IP core
The fast track development and 24x7 operations have put tremendous pressure on the servers, networking systems and communication equipments. It has become necessary that these systems should operate reliably irrespective of the change in external operating environment like the temperature, humidity, and power fluctuations or, on chip conditions like on-chip temperature, internal voltage levels etc. Measuring the reliability of these physical systems is must for every operational unit.
Today we present to you the Akeana 1000 Series Processors, a series of High Performance processors IP which is optimized for AI applications and workloads, thus providing a quick AND efficient processing solution for your AI needs.
Last June, we launched the Codasip L110 RISC-V core, introducing the best-in-class solution for power-efficient applications. The L110 is highly competitive in terms of power efficiency and code density. Additionally, it is the first RISC-V core to support easy and risk-free customization while minimizing the verification effort required to bring these customizations to silicon.
The rise of opensource RISC-V CPU Instruction Set Architecture (ISA) has led many developers to consider migrating from existing popular computer architectures like x86, Arm, MIPS and more to RISC-V CPU ISA. This transition offers various advantages, including an open-source framework and extensive community support.
In this article, we go through a formal-based, easy-to-deploy RISC-V processor verification application. We show how, together with a RISC-V ISA golden model and RISC-V compliance automatically generated checks, we can efficiently target bugs that would be out of reach for simulation.
Christoffer Dall, Arm
