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Vendor:
Xilinx, Inc.
Category:
System Controller
XPS External Peripheral Controller
This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC).
Overview
This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the Processor Local Bus (PLB) and the external synchronous and/or asynchronous peripheral devices.
Key features
- Connects as a 32-bit slave on PLB V4.6 buses of 32-bit, 64-bit or 128-bit
- PLB interface with byte enable support
- Parameterized support of up to four external peripheral devices with each device configured with separate base address and high address range
- Supports both synchronous and asynchronous access modes of peripheral devices with the support for a separate clock domain for synchronous peripheral devices
- Supports both multiplexed and non-multiplexed address and data buses
Specifications
Identity
Part Number
XPS External Peripheral Controller
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about system controller IP cores
What is XPS External Peripheral Controller?
XPS External Peripheral Controller is a System Controller IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this System Controller?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this System Controller IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.