RISC-V CPU IP

Tenstorrent’s TT-Ascalon™ X is an Out-of-Order, superscalar, 8-wide decode processor based on the RISC-V RVA23 profile, co-designed and optimized with Tenstorrent Tensix IP to provide the highest performance possible (>18 SPECint2006 / GHz) while maintaining area and power efficiency. TT-Ascalon™ can be combined with your IP for optimized solutions for next generation AI/ML compute and beyond. TT Ascalon™ X Cores are encapsulated inside the TT-Ascalon™ Cluster, which coherently connects all cores with shareable L2 cache and interfaces to the memory subsystem.

Ideal Use Cases

TT-Ascalon™ is a compute solution for High Performance Compute SoCs targeting Cloud Servers, Data Centers, Wireless Communications, Automotive ADAS/AV, and Client Computing devices. TT-Ascalon™ can be combined with your IP for building accelerated compute processors for next generation workloads.

TT-Ascalon™ X Cluster Features

• Consists of up to 8 RISC-V RVA23 compliant TT Ascalon™ X Cores for maximum performance
• Shared configurable L2 cache
• Cache coherent cluster
• RISC-V compliant Advanced Interrupt Architecture (AIA)
• RISC-V compliant Trace and Debug unit
• CHI-E coherent and AXI5-LITE non-coherent interfaces
• Support for Trusted Execution Environment

Along with the TT-Ascalon™ X Cluster, additional IPs are available to provide a comprehensive solution
Advanced Platform Interrupt Controller
IOMMU

TT-Ascalon™ X Core Features

• RISC-V RVA23 Compliant
• > 18 SPECint2006 / GHz
• 8-wide decode unit
• Advanced branch predictor
• Large L1 cache
• Shared configurable L2 cache
• RVV 1.0 compliant vector unit
• Dual 256b-wide vector units