CAST Enhances Serial Memory Controller IP with Encryption, Low-Power, and ASIL-Ready Options

Production-proven xSPI, HyperBus, and Xccela controller adds AES encryption, AMBA^® power-state management, and programmable delay tuning

Woodcliff Lake, NJ — July 21, 2026 — Semiconductor intellectual property provider CAST today announced an enhanced version of its xSPI-MC Serial Memory Controller IP core, providing ASIC and FPGA designers with a more capable, lower-risk way to connect to, boot from, and access today’s diverse external serial memories.

The upgraded xSPI-MC core supports JEDEC xSPI, HyperBus™, Xccela™, and many proprietary SPI memory interfaces used with Serial NOR, Serial NAND, PSRAM, and HyperRAM™ devices. The controller works with 1x, 2x, 4x QSPI, 8x OSPI or twin-quad, and 16x serial-memory interfaces, and supports flexible system access through XIP, AIP where applicable, DMA, Boot-Image Copy, and register-driven modes.

Although the xSPI standard helps bring order to serial memory interfaces, SoC teams still face practical differences across memory vendors, profiles, command sets, latency cycles, transfer widths, and SDR or DDR operation. CAST’s runtime-programmable protocol engine and auto-configuration capabilities help reduce this integration risk, especially when memory choices change late in a project or when a single system must support multiple memory types.

New capabilities in the xSPI-MC core include:

• Optional AES-128 CTR encryption
• Standard AMBA^® P-channel power-state management with an optional Q-channel wrapper
• Controls for configuring programmable input delay lines across all operating modes, including SDR/DDR, 1x–16x, and high- or low-speed operation, dynamically programmable at run time or during initialization and calibration

Together, these features help system developers protect off-chip firmware and data, reduce idle and standby power, and improve timing margin across different memory devices, boards, and implementation technologies.

The original production-proven xSPI-MC core has been licensed by multiple customers—including repeat licensees—and early customers are already designing in the newly added features. These features make the core an even stronger fit for virtually any SoC using serial memory, from IoT to automotive and industrial applications.

“External serial memories are used in more systems than ever, but customers now need more than basic flash access,” said Evan Price, product manager at CAST. “They want to protect firmware and data stored off-chip, reduce power between short bursts of memory activity, and close timing reliably as interfaces move to faster DDR Octal and 16-bit operation. This enhanced xSPI-MC core addresses these needs while preserving the configurability, soft-PHY portability, and implementation support that customers expect from CAST.”

The new low-power capabilities are especially useful for IoT and sensor-node designs that boot or fetch data from external memory, then spend long periods in sleep or idle states. Automotive ECUs, industrial controllers, secure POS terminal MCUs, 4G/5G cellular devices, and accelerator-based systems such as NPUs can leverage the same capabilities to combine fast external memory access with lower standby power and reduced software overhead.

For applications where external memory may contain valuable firmware, configuration data, or proprietary code, optional AES-CTR encryption enables xSPI-MC to encrypt data before it is stored externally and decrypt it on the fly during supported controller accesses. This helps make copied external-memory contents unusable without the corresponding key material in the target SoC or FPGA.

The controller includes a synthesizable, process-independent soft PHY and requires no process-specific modules. For high-speed operation, programmable delay lines allow fine adjustment of the input sample point per DQ and DQS line, helping compensate for board-level skew, memory timing differences, and implementation variation.

Optional Safety-Enhanced versions of xSPI-MC support ASIL B, ASIL C, and ASIL D Ready configurations for automotive and other safety-related systems. These versions help customers integrate the controller into ISO 26262-oriented SoC safety systems by adding safety mechanisms such as redundancy and CRC and including the Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA), and the ASIL-D Ready certificate issued by SGS-TÜV Saar GmbH.

Explore CAST IP:

• xSPI, HyperBus™, and Xccela™ Serial Memory Controller

Availability

The enhanced xSPI-MC xSPI, HyperBus, & Xccela Serial Memory Controller IP core is available now for ASIC and FPGA implementations. It is delivered in synthesizable Verilog RTL or targeted FPGA netlist form with a verification environment, user documentation, sample timing constraints, and optional technology-mapping support. The optional Safety-Enhanced versions also include safety documentation and evidence of certification.

See the xSPI-MC product page for details and representative implementation results, and please contact CAST for technical questions, evaluation options, and pricing.

About CAST

Computer Aided Software Technologies, Inc. (CAST) is a silicon IP provider founded in 1993. The company’s ASIC and FPGA IP product line includes microcontrollers and processors; compression engines for data, images, and video; interfaces for automotive, aerospace, and other applications; networking stacks and offloading engines; various common peripheral devices; security primitives and comprehensive SoC security modules. Learn more by visiting www.cast-inc.com.

Engineered by Beyond Semiconductor.