Hitting the Memory Wall:Why Cache Miss Tolerance Defines CPU Performance Now
This article shares our experience using Google’s FlatBuffers library as a memory subsystem stress test on the Andes AX46MPV RISC-V core.
Vendor:
StarFive
Category:
CPU
High-performance, commercial-grade RISC-V CPU Core IP
Commercial-grade 64-bit RISC-V CPU IP that is RVA23 Profile compliant, supports Vector and Vector Crypto extensions, and enables high-performance applications.
Overview
Dubhe-100 is a commercial-grade 64-bit RISC-V CPU IP that is RVA23 Profile compliant, supports Vector and Vector Crypto extensions, and enables high-performance applications.
Design Specifications
- SPECint2006: 15/GHz
- Dhrystone v2.2: 10.0/MHz (Legal)
- ISA：RV64GCBVH
- 15-stage pipeline, 6-issue
- Superscalar, deep out-of-order execution
- Support Multi-core cache coherence
- Support instruction fusion
- Support AIA1.0
Key features
HPM
- RISC-V standard HPM support
- Micro-architecture level analysis and performance tuning
PMP&PMA
- Configurable 16/32/64 PMP supported regions, minimum 4096-byte region size
- Support predefined PMA and Svpbmt
Debug & Trace
- Standard debug module compliant with RISC-V Debug Spec
- Standard Trace module interface compliant with RISC-V Trace Spec
Power Management
- Core-level WFI mechanism
- Core/cluster-level clock gating
- Core/cluster-level low-power states: ON/OFF/Retention
- Cluster-level frequency scaling
TKU
- 512-entry 6-way decode/rename/commit ROB
- 256-entry integer physical register file
- 256-entry floating-point/Vector physical register file
VPU
- 8/16/32/64-bit integer, IEEE754-2008-standard 16/32/64-bit floating-point and BF16 floating-point operations
- VLEN=2*DLEN=256
- 2 vector pipeline units
- 2 floating-point pipeline units, sharing VPU
IFU
- Instruction fetch decoupled from branch prediction
- Fetch width: 32 bytes per cycle
- RAS predictor for return instructions
- IJTP predictor for indirect-jump instructions
- TAGE-style predictor for conditional branch instructions
MMU
- Bare, Sv39, and Sv48 modes defined by RISC-V Priv. Spec
- 16-entry fully associative L1 ITLB
- 64-entry fully associative L1 DTLB
- 128-entry 5-way set associative STLB
- Configurable parit check
Software Development
- Bare Metal SDK: GCC/LLCM toolchains; GDB; pre-built OpenOCD; example projects
- Linux SDK: Yocto-based; Kernel 6.18; OpenSBI; UBoot; host development tools
- StarFive StarStudio (pre-built IDE)
Block Diagram
Click to open fullscreen
Applications
- AI & Intelligent Computing
- HPC & Data Center
- Intelligent Edge & Infrastructure
Specifications
Identity
Part Number
Dubhe-100
Vendor
StarFive
Type
Silicon IP
Compute
CPU Architecture
RISC-V
Word Length
64-bit
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
China
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Frequently asked questions about CPU IP cores
What is High-performance, commercial-grade RISC-V CPU Core IP?
High-performance, commercial-grade RISC-V CPU Core IP is a CPU IP core from StarFive listed on Semi IP Hub.
How should engineers evaluate this CPU?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this CPU IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.