2-channel Input Capture peripheral device
- Timers & Watchdogs
- silicon-proven
- now
System peripheral IP cores are essential building blocks in modern SoC and ASIC designs, providing control, management, and support functions for the overall system operation.
This category includes a wide range of peripheral functions such as DMA controllers, interrupt controllers, monitoring and health management blocks, power management controllers, storage-related controllers, system controllers, and timers & watchdogs. These IP cores help coordinate data movement, system supervision, power optimization, fault detection, and overall platform management.
This catalog allows you to explore and compare system peripheral IP cores from leading vendors based on functionality, performance, power consumption, and process node compatibility.
Whether you are designing embedded systems, automotive platforms, or industrial controllers, you can find the right peripheral IP to support your system architecture.
2-channel Input Capture peripheral device
HCLSATAHC26113G core handles data movement between system memory and a SATA device.
The IntelliProp SATA "Y" Bridge design (IPP-SA111A-BR) provides SATA compliant connections per SATA-IO 3.3 and a standard SATA in…
The IntelliProp IPC-BL109A-RD SATA RAID Core is a hardware design block written in HDL that performs RAID 0 operations to provide…
Intel™ Programmable Interrupt Controller
The AL8259 core is the VHDL model of the Intel™ 8259 Programmable Interrupt Controller used in Intel microprocessor systems to co…
SATA "Y" RAID Bridge without NCQ
The IntelliProp IPP-SA112A-BR SATA “Y” Bridge with RAID design provides SATA compliant connections and a standard SATA interface …
DTI_DMA control the DMA transfers data between different points in the memory space without intervention of the CPU.
The Mailbox IP is the communication channel between the internal system and the host processors.
The Basic Timer consists of a 32-bit auto-reload counter driven by a programmable pre-scaler.
The Adv_Timer (-control Timers) consist of a 32-bit auto-reload counter driven by a programmable prescaler.
The RTC (Real Time Clock) provides an automatic wake-up to manage all low-power modes.
The WWDG (WindowWatchdog) is used to detect the occurrence of a software fault, usually generated by external interference or by …
The IWDG (Independent Watchdog) is suited to applications which require the watchdog to run as a totally independent process outs…
Direct Memory Access Controller
The uDMA (Micro Direct Memory Access) controller serves as a hardware approach for direct data transfers between peripherals/memo…
SD Card Input/Output Protocol Controller
SDIO protocol is evolved and upgraded from the SD card protocol.
Compliant to NVM Express 1.4 specification
NVMe Gen5 Controller - Enhances data transfer speeds and reduces latency for storage systems
The NVMe Gen 5 Controller is engineered to harness the power of PCIe Gen 5, delivering up to 32 GT/s per lane for significantly f…
Simulation VIP for SD CARD and SDIO
In production since 2012 for many production designs.SD CARD Cadence Verification IP (VIP) upgrades the SD CARD and SDIO verifica…
The Cadence® Verification IP (VIP) for NVMe is part of Cadence's storage interface VIP portfolio.
Data Movement Engine - Turnkey network compute subsystem for data movement applications.
Physical AI platforms interpret their surroundings using a diverse array of sensors, generating data that must be seamlessly tran…