NVMe IP core -- Directly connect PCIe SSD without external memory

NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without need CPU/OS and External DDR memory. It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.

NVMeG4 IP including PCIe Gen4 Soft IP inside enable the NVMe SSD interface for non-embedded PCIe Gen4 Hard IP Devices. Break the barriers of NVMe interface, Allow to build multi-channel RAID system with very high performance and lowest possible FPGA resources consumption. Learn more about NVMeG4 IP
This IP core license includes the reference design for AMD FPGA boards. It helps you to reduce development time and cost.

• raNVMe-IP (Random Access) is the new generation of NVMe-IP series which is intentionally optimized for random access. raNVMe-IP can achieve more than 500K IOPS for random write access on high performance NVMe SSD without CPU intervention. Ideal for the application which requires multiple access to NVMe SSD with best performance. Learn more about raNVMe IP
• muNVMe-IP (Multi User) is pure hardware logic solutions for very high throughput, multiple data streaming access to NVMe SSD simultaneously without CPU. Simplify your system complexity and maximize performance.
• rmNVMe-IP (Random Access & Multi User) is very high performance NVMe Host Controller which is highly optimized for high-IOPS random access applications. rmNVMe-IP supports multiple user interfaces, each user can simultaneously read/write to a single NVMe SSD at the same time.Learn more about rmNVMe IP

• Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
• Simple user control I/F and FIFO interface for data port 
• Direct connect to Integrated Block for PCI Express from AMD by using 128-bit bus interface
• Include 256 Kbyte RAM to be data buffer
• Support commands: IDENTIFY, WRITE, READ, Shutdown, SMART,Secure Erase and Flush
  • Optional Support: Write Zero, Sanitize (please ask us)
• Supported NVMe device
  • Base Class Code:01h (mass storage), Sub Class Code:08h (Non-volatile), Programming Interface:02h (NVMHCI)
  • MPSMIN (Memory Page Size Minimum): 0 (4Kbyte)
  • MDTS (Maximum Data Transfer Size): 0 (no limitation) or at least 5 (128 Kbyte)
  • LBA unit: 512 byte or 4096 byte
• exFAT & FAT32 file system management without CPU usage (Option)
• URAM support for UltraScale+ device family to reduce BRAM resource usage (Option)
  • 66 BRAM Tiles >> 8 URAM + 2 BRAM Tiles with URAM version
• Support PCIe Switch (Customize support, please ask us)
• Reference design with AB18-PCIeX16、, AB17-M2FMC, AB19-M2PCI and AB20-U2PCI adapter board are available for AMD FPGA boards