Partial Reconfiguration Decoupler IP
Xilinx, Inc.
•
HQ:
USA
The Partial Reconfiguration (PR) Decoupler IP provides logical isolation capabilities for PR designs.
- System Controller
Compare 443 System Peripheral IP Cores from 79 vendors
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Partial Reconfiguration Controller
Xilinx, Inc.• HQ: USAThe Partial Reconfiguration Controller (PRC) IP provides management functions for Partial Reconfiguration designs.
- System Controller
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Xilinx, Inc.• HQ: USA
The LogiCORE™ JTAG to AXI Master IP core is a customizable core that can generate the AXI transactions and drive the AXI signals …
- Debug Trace
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DO-254 Soft Error Mitigation Controller 1.01a
Logicircuit, Inc.• HQ: USAThe Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification.
- Monitoring
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SATA Device Controller on Kintex 7
Logic Design Solutions• HQ: FRANCEThe LDS SATA 3 DEVICE XK7 IP incorporates the Command Layer, Transport layer, the Link layer and the PHY layer on a Xilinx Kintex…
- SATA Controller
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Xilinx, Inc.• HQ: USA
The LogiCORE™ IP Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in …
- Debug Trace
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LogiCore AXI Traffic Generator
Xilinx, Inc.• HQ: USAIncluded at no additional charge with Vivado Design and System edition of software.
- Debug Trace
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Xilinx, Inc.• HQ: USA
Included at no additional charge with ISE™ Embedded, System Edition software Xilinx provides AXI Exerciser IP which as AXI Master…
- Debug Trace
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Integrated Logic Analyzer (ILA)
Xilinx, Inc.• HQ: USAThe customizable Integrated Logic Analyzer (ILA) IP core is a logic analyzer core that can be used to monitor the internal signal…
- Debug Trace
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Xilinx, Inc.• HQ: USA
Included at no additional charge with ISE Embedded, Vivado Design and System Edition software AXI Performance Monitor has the cap…
- Monitoring
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Xilinx, Inc.• HQ: USA
Remote Debug using Vivado Design Suite Xilinx Virtual Cable (XVC) is a TCP/IP-based protocol that acts like a JTAG cable and prov…
- Debug Trace
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Xilinx, Inc.• HQ: USA
Mutex provides a mechanism for mutual exclusion to enable one process to gain exclusive access to a particular resource in a mult…
- System Controller
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Xilinx, Inc.• HQ: USA
Mailbox features a bi-directional communication channel between two processors.
- System Controller
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Xilinx, Inc.• HQ: USA
The ChipScope™ AXI Monitor core is designed to monitor and debug AXI interfaces.
- Debug Trace
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Xilinx, Inc.• HQ: USA
The AXI Video Direct Memory Access (AXI VDMA) core is a soft Xilinx IP core that provides high-bandwidth direct memory access bet…
- DMA
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Xilinx, Inc.• HQ: USA
This document describes the specifications for a Microcontroller Bus Architecture (AMBA®) specification’s eXtensible Interface (A…
- Timers & Watchdogs
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Xilinx, Inc.• HQ: USA
The eXtensible Lite (AXI) Timebase Watchdog Timer is a 32-bit peripheral that provides a 32-bit free-running timebase and watchdo…
- Timers & Watchdogs
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AXI SystemACE Interface Controller
Xilinx, Inc.• HQ: USAThe AXI System ACE™ Interface Controller (AXI SYSACE) is the interface between the AMBA® AXI4 Lite and the Microprocessor Unit (M…
- System Controller
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Xilinx, Inc.• HQ: USA
The LogiCORE™ IP AXI Interrupt Controller (AXI INTC) core concentrates multiple interrupt inputs from peripheral devices to a sin…
- Interrupt Controller
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Xilinx, Inc.• HQ: USA
The AXI Hardware ICAP enables an embedded microprocessor, such as MicroBlaze, to read and write the FPGA configuration memory thr…
- System Controller