Overview
Platform Management Core IP adds two key power-management functions to Platform Manager: Fault Logging and Enhanced Closed-loop Trim.
The Fault Logging function of this IP block supports the ability to log the Platform Manager’s analog and CPLD I/O states to an external flash memory device. Logic for logging and tracking multiple faults is supported, so that logged faults are not overwritten as a result of power cycling. The recorded faults may be accessed over a user SPI port provided for this purpose.
Enhanced closed-Loop trim expands on the on-chip hardware trim engine by providing the ability to set trim targets in real-time through either an I2C or SPI serial interface, as well as the new feature of being able to select individual channels for trimming operations. In addition, this IP function provides the option of supporting up to two VID trim channels, where up to 16 distinct trim targets can be dynamically selected through a 4-bit binary code.
The Lattice Platform Manager Core IP is widely parameterizable and supports a wide range of interface options, as well as importing configuration data from PAC-Designer.
Learn more about System Controller IP core
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First announced on May 4, 2026, the acquisition creates the industry's most complete secure management and control platform.
The acquisition brings together Lattice’s industry-leading low power FPGAs with AMI’s industry‑leading platform firmware and infrastructure manageability solutions for cloud and AI to create a complete portfolio of secure management and control solutions.
The collaboration demonstrates a real-time AI sensor fusion architecture that integrates TI mmWave radar and camera sensors using NVIDIA Holoscan Sensor Bridge running on Lattice’s low power FPGA. The FPGA acts as a companion chip delivering synchronized sensor data directly into GPU-accessible memory to enable low-latency and robust perception for robotics and industrial edge AI applications.
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Lattice Semiconductor today announced that the company expanded its small FPGA portfolio with new, high I/O density options in the Lattice Certus™-NX FPGA and Lattice MachXO5™-NX FPGA device families.
