AMD Receives All Necessary Approvals for Proposed Acquisition of Xilinx
AMD (NASDAQ: AMD) today announced that it has received approval from all necessary authorities to proceed with the acquisition of Xilinx, Inc. (NASDAQ: XLNX).
Vendor:
Xilinx, Inc.
Category:
Monitoring
Partial Reconfiguration Bitstream Monitor IP
The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design.
Overview
The Partial Reconfiguration (PR) Bitstream Monitor can be used to identify partial bitstreams as they flow through the design. This information can be used for debugging or to help manage system applications such as blocking bitstream loads. Identifiers embedded at key places in partial bitstreams are extracted are reported by the core. This information can be passed to Vivado HW Debugger using an ILA core to work out what partial bitstream was fetched, if it was fetched in its entirety, and how far through the datapath it went.
Key features
- ICAP, AXI4MM (partial support), AXI4-Lite and Generic datapaths supported
- Partial Bitstreams can be traced in the Configuration Engine
- Live and buffered status
- Optional Signal based or AXI4-Lite control
- Optional AXI4-Lite status (signal status is always available)
Specifications
Identity
Part Number
Partial Reconfiguration Bitstream Monitor IP
Vendor
Xilinx, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about system monitoring IP cores
What is Partial Reconfiguration Bitstream Monitor IP?
Partial Reconfiguration Bitstream Monitor IP is a Monitoring IP core from Xilinx, Inc. listed on Semi IP Hub.
How should engineers evaluate this Monitoring?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Monitoring IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.