The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash.
The Inline Decrypter IP Core enables on-the-fly execution of encrypted code from Flash. It is often used to protect the source code from decompiling or reverse engineering.
This solution includes a highly optimized implementation of the Advanced Encryption Standard (AES) algorithm. The IP can be packaged optionally with a xSPI Controller. With the Inline Decrypter IP Core, our customers can take advantage of our expertise in ASIC and FPGA design, cryptography & security applications and the development & integration of re-usable cores & high-level IP solutions. DPA countermeasures option available for applications requiring higher level of security with a very good protection against SPA (Simple Power Analysis) and DPA (Differential Power Analysis).
Implementation aspects
The unique architecture enables a high level of flexibility. The throughput and features required by a specific application can be taken into account in order to select the most optimal configuration for any FPGA or ASIC technology. The single RTL database for all configurations is a guarantee of liability and integration is made very easy due to standard interface (AMBA AHB).
Note: some files may require an NDA depending on provider policy.
Inline Decrypter IP Core is a Symmetric Crypto IP core from Secure-IC listed on Semi IP Hub.
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.