Vendor: Texplained Category: Root Of Trust

Anti-Counterfeiting Digital IP - Self-aware and Anti-bypass

Protection of the embedded secrets against professional hackers stealing actions Protection of Non-Volatile-Memory to make sure t…

Overview

  • Protection of the embedded secrets against professional hackers stealing actions
  • Protection of Non-Volatile-Memory to make sure that pirates:
    •  Do not access the code (boot loader, test functions) which could be used to extract the embedded software or data
    •  Can not extract the embedded software which would allow them to:
      •  Gain information to be able to easily perform cheaper attacks
      •  Emulate the code on another device
    •  Have no access to user data
  •  Great efficiency: needs very little silicon area, consumes very low energy and does not degrade the IC performance
  •  100% Hardware based: does not require extra-software design as it relies on the IC itself

Key features

  • Texplained’s countermeasure is schematically composed of two main blocs:
  • 1. The Detection Module detects the attack « on the fly »
  • => Its checks the execution flow of the software to detect if a Hardware attack is in progress
  • 2. The Defense Module reacts to the attack by preventing the striker to obtain the code in the NVW
  • => It is highly linked to the architecture of the chip itself, then fully flexible to adapt any Hw architecture
  • This module brings self-awareness to the chip, avoiding the development of a specific sw security

Block Diagram

NVM Defender block diagram

Benefits

  •  EFFECTIVENESS against the most common invasive attack:
    •  Protection against NVM read-out
    •  Protection of chip designer’s assets and user code
  • => Prevents from counterfeiting, emulation / copy, cloning (off-branded and illegal copies)
  • - EASY-INTEGRATION:
    • - 100% Standard Cells-based design, fully integrable in the digital core
      • => No analog parts involved
    • - 100% hardware CM: no Sw involved in both modules (Detection and Defense)
    • - 0% sw development needed for the integration of the countermeasure in the design
  • => No additional costs for sw development
  • - COST-EFFECTIVENESS:
    • - Small footprint (only a few standard cells)
    • - No impact on the chip performance (passive monitoring)
    • - Insignificant power consumption
  • => Very favorable Security / Cost ratio

Applications

  • e-Gov
  • IoT
  • Pay TV
  • Consoles & printers peripherals
  • Access Control
  • Smart meters
  • Ticketing

What’s Included?

  • Architecture of the Countermeasure
  • Design Specification of the Detection Module
  • Adaptation of the Countermeasure to the chip’s architecture
  • Support on the integration of the Countermeasure

Specifications

Identity

Part Number
NVM Defender
Vendor
Texplained
Type
Silicon IP

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Texplained
HQ: France

Learn more about Root Of Trust IP core

Neotion partners with Texplained creating stronger Secure by Design ICs

NEOTION, a leading provider of secure solutions for Pay-Tv industry and recently targeting the IoT market, has selected Texplained, another French company with a team of experts in Secure ICs Architecture and Reverse Engineering, for a better level of security by design into its next in house chipset generation.

Frequently asked questions about Root of Trust IP cores

What is Anti-Counterfeiting Digital IP - Self-aware and Anti-bypass?

Anti-Counterfeiting Digital IP - Self-aware and Anti-bypass is a Root Of Trust IP core from Texplained listed on Semi IP Hub.

How should engineers evaluate this Root Of Trust?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Root Of Trust IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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