This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1.
- SHA1
Security IP cores provide the hardware foundation required to protect modern SoC and ASIC designs against an increasingly sophisticated threat landscape. They enable secure data processing, trusted device operation, intellectual property protection, and compliance with industry security standards.
This category includes a comprehensive range of security technologies, from cryptography engines for encryption, decryption, hashing, and authentication, to interface security solutions that protect data in transit. It also covers key management IP for secure key generation and storage, root of trust implementations that establish a trusted security foundation, secure processing architectures for isolated execution of sensitive workloads, and side-channel protection technologies designed to mitigate power, timing, electromagnetic, and fault-injection attacks.
This catalog allows you to explore and compare Security IP cores from leading vendors based on security capabilities, performance, certification readiness, attack resistance, silicon maturity, and process node compatibility.
Whether you are developing connected IoT devices, automotive platforms, industrial equipment, consumer electronics, networking infrastructure, or cloud and edge computing systems, you can identify the security IP solutions needed to build resilient and trustworthy semiconductor products.
This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1.
This core family implements various aspects of the AES ( Encryption Standard) algorithm.
This core is a full implementation of the Triple DES encryption algorithm.
CryptoManager Root of Trust for Use with the Caliptra Specification
Root of Trust and Security Orchestration for Caliptra-based SoCs
Open And Secure Distributed Security Architecture
SiFive Shield is a comprehensive portfolio of hardware security technologies designed for RISC-V processors and SoCs.
Multi-world Hardware Isolation System IP for System Security
Delivers advanced execution environment capabilities and hardware-enforced isolation to RISC-V systems
Composed of three dedicated HW IP cores (PolyCore, KeccakCore, MaskCore) and the software stack
co-processor supporting NIST’s selected Post-Quantum Cryptography (PQC) standards
Supports the polynomial arithmetic required by lattice-based cryptography algorithms
The Keccak IP core supports Keccak-based hash functions, including the SHA3 and SHAKE families.
Embedded HSM (Root of Trust) with Arm Cortex-M33 Processor
Automotive Grade ISO 26262 ASIL-B
The I/O Physical Memory Protection (IOPMP) unit is a hardware-based access control mechanism designed to safeguard memory regions…
PUF-based Post-Quantum Cryptography (PQC) Solution
As quantum computing advances at an unprecedented pace, traditional cryptographic systems are encountering new challenges.
Secure Storage Solution for OTP IP
The Synopsys Secure Storage Solution for OTP is an add-on to Synopsys One-Time Programmable (OTP) Non-Volatile Memory (NVM) IP.
IPSEC AES-256-GCM (Standalone IPsec)
XIP7213E implements the Internet Protocol Security (IPsec) as standardised in RFC4303 and RFC4305.
Advanced DPA- and FIA-Resistant Software Library
The AES-SW library delivers high-performance protection against side-channel (SCA) and fault injection attacks (FIA) through OTA …
Root of Trust IP is a Hardware Secure Module (HSM) solution that provides the security foundation for processors and System on Ch…
100G / 200G / 400G / 800G / 1.6T MACsec
Ethernet Layer 2 Security solution for High speed applications The MACsec IP provides Ethernet Layer 2 Security for port authenti…
Ultra compact Ethernet Layer 2 Security solution The MACsec IP provides Ethernet Layer 2 Security for port authentication, data c…
MSP7-32 MACsec IP core for FPGA or ASIC
Implementation of the LAN security standard IEEE 802.1ae (MACsec) requires the NIST standard AES cipher in the GCM mode for encry…