Vendor: Ocean Logic Pty Ltd Category: Symmetric Crypto

Triple DES core

This core is a full implementation of the Triple DES encryption algorithm.

Overview

This core is a full implementation of the Triple DES encryption algorithm. Both encryption and decryption are supported. Simple, fully synchronous design with low gate count.

The X_3DES core is a full hardware implementation of the triple DES algorithm as described in the X9.52 standard, suitable for a variety of applications. 
 
The triple DES algorithm was proposed by IBM when it became clear that the security of the DES had been compromised by advances in computer technology. 
 
Compared to the DES algorithm, the triple DES algorithm provides a much higher level of security. 
 
Each triple DES encryption/decryption operation (as specified in ANSI X9.52) is a compound operation of the DES encryption and decryption operations. 

Key features

  • Implemented according to the X9.52 standard
  • Implementation based on NIST certified DES core
  • Also available in CBC, CFB and OFB modes.
  • 112 or 168 bits keys supported.
  • Both encryption and decryption supported.
  • Encryption and decryption performed in 48 clock cycles.
  • No dead cycles for key loading or mode switching. .
  • Encryption or decryption can start every 16 or 48 cycles, depending on the version.
  • Fully synchronous design.
  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • Test benches provided.
  • Xilinx netlist available

Block Diagram

Applications

  • Electronic financial transactions.
  • Secure communications.
  • Secure video surveillance systems.
  • Encrypted data storage.

What’s Included?

  • Netlist available for most Xilinx and Altera devices.
  • Synthesizable VHDL or Verilog RTL.
  • Complete HDL testbench.

Specifications

Identity

Part Number
OL_3DES
Vendor
Ocean Logic Pty Ltd
Type
Silicon IP

Files

Note: some files may require an NDA depending on provider policy.

Provider

HQ: Australia

Learn more about Symmetric Crypto IP core

From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs

This paper attempts to address and reconcile two different issues: the existence of multiple numerical data formats (such as int8, bfloat16, fp8, etc., often non optimal for the application and not directly compatible with one another) and the necessity to reduce their bandwidth requirements, especially in the case of power hungry and slow DRAM.

Efficient FIR filtering with Bit Layer Multiply Accumulator

Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255.

An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning

This paper discusses the hardware implementation of an encoder and a decoder for the QOI lossless RGB image format. Some results are given for the AMD/Xilinx architecture, reaching over 800 Mpixels/s in Ultrascale+ and more than 4K@30 in Artix-7. A compression improvement up to ~15% is also observed when natural images are scanned along a Hilbert curve instead of the normal raster order.

Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference

This paper discusses three basic blocks for the inference of convolutional neural networks (CNNs). Pyramid Vector Quantization (PVQ) is discussed as an effective quantizer for CNNs weights resulting in highly sparse and compressible networks. Properties of PVQ are exploited for the elimination of multipliers during inference while maintaining high performance. The result is then extended to any other quantized weights. The Tiny Yolo v3 CNN is used to compare such basic blocks.

Frequently asked questions about Symmetric Cryptography IP cores

What is Triple DES core?

Triple DES core is a Symmetric Crypto IP core from Ocean Logic Pty Ltd listed on Semi IP Hub.

How should engineers evaluate this Symmetric Crypto?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Symmetric Crypto IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP