Embedded HSM (Root of Trust) with Arm Cortex-M33 Processor

The Rambus CryptoManager RT-648 Root of Trust is a fully-programmable hardware security core offering security by design for automotive applications. As the connected nature of automobiles evolves, device architects face a growing array of emerging security threats. Whether V2X, ADAS, infotainment, or other applications, one constant is the need for a hardware Root of Trust-based security implementation.

Based on a 32-bit Arm Cortex-M33 siloed and layered secure co-processor, along with dedicated secure memories, the ASIL-B compliant RT-648 features a number of high-capability cryptographic accelerators like AES (all modes), HMAC-SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST-compliant Random Bit Generator and fast DMA. It also provides Chinese cipher algorithms SM2, SM3 and SM4 and Quantum Safe Crypto acceleration with ML-KEM, ML-DSA, SLH-DSA in all modes.

How the Embedded HSM Works

The Root of Trust RT-648 is a siloed hardware security block for integration into automotive semiconductors, offering secure execution of authenticated user applications, tamper detection and protection, secure storage and handling of keys and security assets, and resistance to side-channel attacks. The RT-648 core implements hardware and software safety mechanisms to exceed ASIL-B safety integrity levels.

The core is easily integrated with industry-standard interfaces and system architectures and includes standard hardware cryptographic cores. Access to crypto modules, keys, memory ranges, I/O, and other resources is enforced in hardware. Critical operations, including key derivation and storage, are performed in hardware with no access by software.

The RT-648 is built around a 32-bit Arm Cortex-M33 processor, which provides a strong integration into the Arm CSS framework, while also working with other common main processor architectures including RISC-V, x86 and others. The tight integration with Arm CSS reduces integration effort, accelerates deployment, and builds on a proven ecosystem for scalable platform security.

The secure CPU runs signed code modules called containers, which include permissions and security-related metadata. These containers can implement standard security functionality provided by Rambus, or complete customer-specific security applications, including key and data provisioning, security protocols, biometric applications, secure boot, secure firmware update, and many more.

• ISO 26262 ASIL-B compliant hardware security core
• 32-bit Arm Cortex-M33 secure processor
• Multi-layered security model protects all core components against a wide range of attacks
• Security model includes hierarchical privilege model, secure key management policy, hardware-enforced isolation/access control/protection, error management policy
• Standard hardware cryptographic accelerators, including AES (all modes), HMAC, SHA-2 (all modes), RSA up to 4096 bits, ECC up to 521 bits, a NIST SP 800-90a/b/c Random Bit Generator, AXI Interface and Fast DMA capability.
• Chinese OSCCA SM2-SM3-SM4 hardware crypto accelerators
• Quantum Safe hardware cryptographic accelerators, including ML-KEM, ML-DSA, SLH-DSA all modes
• In addition to crypto modules, a wide range of security modules such as canary logic for protection against glitching and overclocking, secure key derivation and key transport, life cycle management, secure test and debug, feature management are implemented

Complete Documentation

• Hardware integration guide
• Hardware and software reference manuals
• Programming guides
• ASIL-B FMEDA and Safety Manual

Tools and Scripts

• Verilog for synthesis and simulation
• All scripts and support files needed for standard EDA tool flows

Integration Deliverables

• Complete verification test bench and comprehensive set of test vectors
• Boot loader and firmware, including secure RTOS and security monitor
• HLOS APIs for accessing capabilities
• Complete development environment, including compiler, assembler, debugger, simulator, reference code