AES core

This core family implements various aspects of the AES (Advanced Encryption Standard) algorithm. Simple, fully synchronous design with low gate count.

The OL_AES core family is a hardware implementation of various aspects of the AES algorithm as described in NIST’s released documentation, suitable for a variety of applications.

The AES algorithm was selected by NIST on October 20, 2000 amongst a group of competing algorithms.

The algorithm chosen by NIST, Rijndael offers strong and secure encryption with the added flexibility of variable key block sizes.

Compared to the DES and the triple DES algorithms AES provides an even higher level of security.

An AES encryption operation consists in the transformation of a 128 bits block into a block of the same size.

The encryption key can be chosen among three different sizes: 128, 192 or 256 bit. The key is expanded during cryptographic operations.

• Implemented according to the FIPS 197 documentation.
• Also available in CBC, CFB and OFB modes.
• Key size of 128, 192 and 256 bits.
• Both encryption and decryption supported.
• Fully synchronous design.
• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx and Altera netlists available.

• Electronic financial transactions. 
• Secure communications. 
• Secure video surveillance systems. 
• Encrypted data storage. 

• Available as fully functional and synthesizable VHDL or Verilog soft-core.
• Test benches provided.
• Xilinx and Altera netlists available.