Vendor: Ocean Logic Pty Ltd Category: Hash / MAC

SHA-1 Processor

This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1.

SHA1 View all specifications

Overview

This core is a fully compliant implementation of the Secure Hash Algorithm, SHA-1. It computes a 160-bit message digest for messages of up to (264 – 1) bits. Simple, fully synchronous design with low gate count.

The OL_SHA core is a fully compliant hardware implementation of the SHA-1 algorithm, suitable for a variety of applications.

The SHA-1 algorithm is based on principles similar to those used by Professor Ronald L. Rivest of MIT when designing the MD4 message digest algorithm, and is closely modeled after that algorithm. It operates on message blocks of 512 bits for which a 160-bit (5 x 32-bit words) digest is produced. Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to form the digest of the whole message.

Key features

  • Suitable for data authentication applications.
  • Fully synchronous design.
  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • Xilinx and Altera netlist available for various devices.

Block Diagram

OL_SHA block diagram

Applications

  • Electronic Funds Transfer. 
  • Authenticated Electronic data transfer. 
  • Encrypted data storage.

What’s Included?

  • Available as fully functional and synthesizable VHDL or Verilog soft-core.
  • Xilinx and Altera netlist available for various devices.

Specifications

Identity

Part Number
OL_SHA
Vendor
Ocean Logic Pty Ltd
Type
Silicon IP

Security

Crypto Algorithm
SHA1

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Ocean Logic Pty Ltd
HQ: Australia

Learn more about Hash / MAC IP core

From a Lossless (~1.5:1) Compression Algorithm for Llama2 7B Weights to Variable Precision, Variable Range, Compressed Numeric Data Types for CNNs and LLMs

This paper attempts to address and reconcile two different issues: the existence of multiple numerical data formats (such as int8, bfloat16, fp8, etc., often non optimal for the application and not directly compatible with one another) and the necessity to reduce their bandwidth requirements, especially in the case of power hungry and slow DRAM.

Efficient FIR filtering with Bit Layer Multiply Accumulator

Bit Layer Multiplier Accumulator (BLMAC) is an efficient method to perform dot products without multiplications that exploits the bit level sparsity of the weights. A total of 1,980,000 low, high, band pass and band stop type I FIR filters were generated by systematically sweeping through the cut off frequencies and by varying the number of taps from 55 to 255.

An 800 Mpixels/s, ~260 LUTs Implementation of the QOI Lossless Image Compression Algorithm and its Improvement through Hilbert Scanning

This paper discusses the hardware implementation of an encoder and a decoder for the QOI lossless RGB image format. Some results are given for the AMD/Xilinx architecture, reaching over 800 Mpixels/s in Ultrascale+ and more than 4K@30 in Artix-7. A compression improvement up to ~15% is also observed when natural images are scanned along a Hilbert curve instead of the normal raster order.

Pyramid Vector Quantization and Bit Level Sparsity in Weights for Efficient Neural Networks Inference

This paper discusses three basic blocks for the inference of convolutional neural networks (CNNs). Pyramid Vector Quantization (PVQ) is discussed as an effective quantizer for CNNs weights resulting in highly sparse and compressible networks. Properties of PVQ are exploited for the elimination of multipliers during inference while maintaining high performance. The result is then extended to any other quantized weights. The Tiny Yolo v3 CNN is used to compare such basic blocks.

Frequently asked questions about Hash / MAC IP cores

What is SHA-1 Processor?

SHA-1 Processor is a Hash / MAC IP core from Ocean Logic Pty Ltd listed on Semi IP Hub.

How should engineers evaluate this Hash / MAC?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Hash / MAC IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

×
Semiconductor IP