This configurable implementation of the XTS-AES algorithm for storage encryption implements the full NIST SP800-38E specification…
- AES
Symmetric Cryptography IP cores implement hardware-based cryptographic functions for trusted SoC and ASIC architectures in modern SoC and ASIC designs.
These IP cores support high-throughput block and stream cipher acceleration for secure data protection, helping designers improve security throughput, reduce CPU overhead, and strengthen system trust anchors
This catalog allows you to compare Symmetric Cryptography IP cores from leading vendors based on security level, throughput, power efficiency, and process node compatibility.
Whether you are designing storage encryption, secure communications, IoT devices, or secure embedded systems, you can find the right Symmetric Cryptography IP for your application.
This configurable implementation of the XTS-AES algorithm for storage encryption implements the full NIST SP800-38E specification…
This implementation of the AES-CCM algorithm implements the full NIST draft SP800-38C specification.
25 Gb/s AES-ECB 128/192/256 Crypto Cores
Concurrent EDA AES cores implement the 128-bit block size NIST FIPS AES Algorithm.
This configurable implementation of the AES-GCM algorithm implements the full NIST draft SP800-38D specification.
Implementation of the new encrypted shared storage media standard IEEE P1619 with AES cipher in the LRW mode.
Implementation of the older drafts standard IEEE P1619 required the NIST standard AES cipher in the LRW mode for encryption (AES-…
The Enhanced AES (Rijndael) IP Core provides numerous building blocks that are used to put together an encryption core for a vari…
High Performance AES-XTS/ECB Core
With the tremendous data and bandwidth growth in our connected world, security is essential to protect private and sensitive data…
AES Authenticated Encryption Accelerator with DPA or with DPA and FIA
The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher accel…
The MVD DVB-CSA Descrambler core allows to decrypt MPEG-TS stream using ETSI specified DVB Common Scrambling Algorithm (CSA2).
Multi-2 Descrambler Supporting BCAS for ISDB-T,TMM in Japan
MEGACAST MULTI2 IP core implements the MULTI2 encryption/decryption algorithms as specified by ISO9979/0009 algorithm register en…
This is a pipelined high throughput AES core capable of starting a new encryption every clock cycle.
This is a high performance pipelined implementation of AES optimized for encryption of uncompressed video on low cost FPGA famili…
The MW_AES core performs the digital baseband function that can be used to protect electronic data.
AES-CCM is an authenticated encryption block cipher mode which provides data confidentiality, integrity and origin authentication…
The Standard AES core family is our mid-rate solution, aimed at applications which require a few hundred Mbps throughput, whilst …
Cryptographic engine using the DES, Triple-DES or AES
The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
On-the-fly decryption engine FRTDEC allows to decrypt on-the-fly AXI traffic based on the read request address information.
The Cryptography Software Library IP offers a comprehensive suite of encryption and certificate processing functions for embedded…
Ultra High Performance AES-GCM/CTR Core
The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence, …