The compact, High-Performance AES-GCM/CTR IP implements the AES-GCM/CTR algorithm as specified in the National Institute of Stand…
- AES
Symmetric Cryptography IP cores implement hardware-based cryptographic functions for trusted SoC and ASIC architectures in modern SoC and ASIC designs.
These IP cores support high-throughput block and stream cipher acceleration for secure data protection, helping designers improve security throughput, reduce CPU overhead, and strengthen system trust anchors
This catalog allows you to compare Symmetric Cryptography IP cores from leading vendors based on security level, throughput, power efficiency, and process node compatibility.
Whether you are designing storage encryption, secure communications, IoT devices, or secure embedded systems, you can find the right Symmetric Cryptography IP for your application.
The compact, High-Performance AES-GCM/CTR IP implements the AES-GCM/CTR algorithm as specified in the National Institute of Stand…
Security Protocol Accelerator for SM3 and SM4 Ciphers
Complex system-on-chip (SoC) requirements can include security at various application layers.
AES encryption transforms plaintext into ciphertext through multiple transformation rounds.
Ultra High Performance AES-XTS/ECB Core
The proliferation and expansion of connected devices, connectivity infrastructure, cloud computing, and artificial intelligence, …
ES256-XTS IP Core (AES256XTSIP) implement the encryption standard (AES) with XEX Tweakable Block Cipher with Ciphertext Stealing …
AES-GCM IP Core for 40Gbit/sec packet data
This state of the art implementation of AES-GCM achieves 40Gbit/sec performance on Virtex 5 FPGAs.
Duplex AES-GCM at 10Gbit/sec for OTN
This state of the art implementation of the AES-GCM algorithm provides privacy and authentication and achieves 10Gbit/sec perform…
This core extends the Algotronix G3 Encryption Standard (AES) core by providing a secure, standardized method for loading cryptog…
eSi-AES is a range of sophisticated AES cores for use in ASIC or FPGA technologies.
LRW3 implements the NIST standard AES cipher in the LRW mode for encryption and decryption.
DES Encryption and Decryption Processor
The IP-ALDES core is the VHDL model of the processor, that performs DES encryption and decryption.
NIST’s ASCON Lightweight Crypto Algorithm Accelerator
The ASCON-IP-41 is an efficient implementation of NIST’s lightweight crypto algorithm family ASCON.
ZUC (128-EEA3 and 128-EIA3) Core
This IP core implements the ZUC stream cipher and the 128-EEA3 encryption and 128-EIA3 authentication algorithms based on it whic…
Advanced Encryption Standard (AES-128) core with AMBA AHB interface
The GRAES core implements the AES-128 symmetric encryption algorithm for high-throughput applications.
AES-GCM - Authenticated Encryption and Decryption
Optimized for high processing throughput, suitable for designs that require increased performance while maintaining efficient use…
AES-GCM Authenticated Encryption and Decryption
Optimized for minimal logic and power usage, making it suitable for designs with stringent FPGA resource or energy constraints.
IP
Cipher coprocess for encryption/decryption of DES/Triple-DES/AES algorithm.
Cipher coprocess for encryption/decryption of DES/Triple-DES/AES algorithm.