UCIe-A PHY for Advanced Package (x64) in TSMC (N7, N6, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) in TSMC (N7, N6, N4P, N5, N3)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
UCIe-S PHY for Standard Package (x16) in Samsung (SF5A, SF4X, SF2)
Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…
The NuLink technology delivers low-power and high-performance D2D IP core products, which support multiple industry standards and…
BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP.
Universal Chiplet Interconnect Express (UCIe™) PHY and Controller
High-bandwidth, low-power and low-latency standardized die-to-die interconnect
45SPCLO UCIe-Class 1-32Gbps Low Power Receiver IP (NRZ)
UCIe-Class receiver macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 70mV sensitivity
45SPCLO UCIe-Class 1-32Gbps Low Power Transmitter IP (NRZ)
UCIe-Class transmitter macro on GF 45SPCLO technology node supporting from 1 to 32Gbps with 800mVpp single ended
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 3nm UCIe-A 32G Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
TSMC 5nm UCIe-A 32G LP Die to Die Interface
Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
Scalable RISC-V CPUs for Data Center, Automotive, and Intelligent Edge
Ncore Cache Coherent Interconnect IP
High-bandwidth, low-latency network-on-chip (NoC) interconnect for rapid modular innovation.
Die-to-Die / Short-Reach SerDes
32 Gbps UCIe-class links with CTLE and CTLE+DFE on GF Fotonix™, under development