NoC IP Listing

Entry-level network-on-chip (NoC) IP for low power and cost efficiency.

• Network-On-Chip
• Silicon Proven
• Available with FlexNoC 5 when Released

The core idea behind the Universal PHY is to enable open chiplets for a broad range of applications.

• BOW

The Die-to-Die Controller IP, optimized for latency, bandwidth, power, and area, enables efficient inter-die connectivity in serv…

• Custom

Automates the creation of resource and power optimized block memories for Xilinx® FPGAs Note: Used as sub-IP within FIFO Generator

• SRAM
• AVAILABLE

JESD204B is a JEDEC interfacing standard for high-speed serial communications of digital radio samples and control data between l…

• JESD204
• Available
• JEDEC JESD204B.01 2012

Xilinx provides a flexible Block Memory Generator core to create compact, high-performance memories running at up to 450 MHz The …

• SRAM

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 3nm
• N3P

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 5nm
• N5A

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• UCIe
• Available on request
• Available

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• UCIe
• Contact the Vendor

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• UCIe
• Available on request
• Available

The UCIe Controller IP encompasses the Die-to-Die Adapter Layer and Protocol Layer for widely used protocols, such as PCI Express…

• UCIe

The Synopsys Die-to-Die Controller IP, optimized for latency, bandwidth, power and area, enables efficient inter-die connectivity…

• Custom
• Available on request
• Available

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 6nm
• N6

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• TSMC
• 3nm
• N3E

Synopsys UCIe PHY IP enables high-bandwidth, low-power and low-latency die-to-die connectivity in a package for hyperscale data c…

• UCIe
• Available on request
• Available

WebM’s G2 VP9 Decoder IP is the latest addition to WebM family of hardware IP products for multimedia system-on-chip designs.

• VP9
• TSMC
• 28nm
• Silicon Proven