Timing Fragility Aware Selective Hardening of RISCV Soft Processors on SRAM Based FPGAs
This paper introduces a timing fragility aware selective hardening methodology for RISCV soft processors implemented on SRAM based FPGAs.
Vendor:
Logicircuit, Inc.
Category:
SRAM
DO-254 Block Memory Generator 1.00a
Automates the creation of resource and power optimized block memories for Xilinx® FPGAs Note: Used as sub-IP within FIFO Generator
Overview
Automates the creation of resource and power optimized block memories for Xilinx® FPGAs Note: Used as sub-IP within FIFO Generator
Key features
- Choice of Native Interface, AXI, or AXI4-Lite
- Example Design helps you get up and running quickly
- Native interface core
- Generates Single-Port RAM, Simple Dual-Port RAM, True Dual-Port RAM, Single-Port ROM, or Dual-Port ROM
- Performance up to 450 MHz
- Data widths from 1 to 4096 bits
- Memory depths from 2 to 128k
- Variable Read-to-Write aspect ratios in Virtex®-7, Kintex®-7, Virtex-6, Virtex-5 and Virtex-4 FPGAs
- Option to optimize for resource or power
- Ability to initialize the memories with pre-defined values
- Supports individual write enable per byte in Virtex-7, Kintex-7, Virtex-6, Virtex-5, Virtex-4, Spartan®-6 and Spartan- 3A / XA DSP with or without parity
- Selectable per-port operating mode: WRITE_FIRST, READ_FIRST or NO_CHANGE
- Support for hard and soft Error Correction (ECC) feature
- AXI interface core
- Generates Dual Port RAM
- Performance up to 300 MHz
- Data widths ranging from 8 to 64 bits
- Common features in Native interface and AXI cores
- Variable port aspect rations for dual-port configurations
- VHDL and Verilog behavioral models optimized for fast simulation times
- Structural simulation model option for precise simulation
Benefits
- Mature source IP has been re-engineered for full DAL-A compliance for airworthiness and design assurance for safety-critical programs, supporting and simplifying the compliance effort at the FPGA level.
What’s Included?
- Encrypted source along with a complete certification data package (CDP) including all artifacts required for chip-level compliance.
Specifications
Identity
Part Number
10129
Vendor
Logicircuit, Inc.
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about SRAM IP cores
What is DO-254 Block Memory Generator 1.00a?
DO-254 Block Memory Generator 1.00a is a SRAM IP core from Logicircuit, Inc. listed on Semi IP Hub.
How should engineers evaluate this SRAM?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this SRAM IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.