DDR Interface IP cores provide the controller, PHY, and calibration technologies required to connect SoCs and ASICs to external DRAM memory devices, enabling high-bandwidth and low-latency memory access for compute-intensive applications.
This category includes IP solutions supporting DDR2, DDR3, DDR4, and DDR5 memory standards. Available implementations may include memory controllers, PHYs, controller-PHY subsystems, training engines, initialization logic, timing management, ECC support, and signal integrity optimization features designed for reliable operation across advanced semiconductor process nodes.
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY Command/Address Block ; UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY compensation block for 171 series (non BOAC); UMC 0.13um HS/FSG Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY Compensation block; UMC 55nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 PHY compensation block; UMC 65nm SP/RVT LowK Logic Process
DDR2 SDRAM Controller
Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…
Synopsys offers a system-level memory interface IP portfolio for SoCs requiring an interface to one or a range of high-performanc…
High-Performance Memory Controller II SDRAM Intel® FPGA IP Core
The High-Performance Memory Controller II SDRAM Intel FPGA IP core handles the complex aspects of using DDR, DDR2, and DDR3 SDRAM…
The DDR multiPHY IP solutions are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3, DDR3L (1.3…
The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR3 and DDR2 SDRAM memor…
Streaming Multi-port SDRAM Memory Controller
The Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory.
Avalon Multi-port SDRAM Memory Controller IP Core
The Microtronix Avalon Multi-port SDRAM Memory Controller IP Core is designed for maximizing the performance of an Altera Nios II…
Fault Tolerant DDR2/DDR3/DDR4 Memory controller
FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.
DDR-I/II/III CONTROLLER IP CORE
DDRI/II/III Memory Controller Core implements an efficient and pipelined interface to DDR-I, DDRII and DDR-III SDRAM devices targ…
DO-254 DDR Memory Controller 1.00a
A dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the …
DO-254 AXI 7-Series DDRx (Limited) 1.00a
Maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interf…
DDR3 SDRAM Controller
SDRAM/SRAM/FLASH Memory Controller
Increasing SoC/ASIC devices' complexity also demands increase in memory bandwidth.
The DDR multiPHYs are mixed-signal PHY IP cores that supply the physical interface to JEDEC standard DDR2, DDR3, LPDDR2, LPDDR3 S…
The DDR3/2 PHY is a mixed-signal IP solution designed to provide DDR 3/2 SDRAM connectivity in a System-On-a-Chip (SOC) design ta…