DDR3/2 PHY - TSMC 40LP25

The DDR3/2 PHY cores are mixed-signal PHY IP cores that supply the complete physical interface to JEDEC standard DDR3 and DDR2 SDRAM memories. The DDR3/2 PHY IP supports the entire range of DDR3 SDRAM speeds, from DDR3-800 through DDR3-2133, with backward compatibility provided for DDR2-667 through DDR2-1066 devices. The PHYs are compiled into a hard macro optimized for specific foundry nodes. Each DDR3/2 PHY is constructed from the following libraries of components: the application-specific SSTL I/O library, a single address/command macroblock and multiple byte-wide data macro blocks instantiated as many times as required to accommodate the memory channel width. Finally, the DDR3/2 PHY includes a PHY Utility Block (PUB) that is supplied as soft IP. The PUB contains the circuitry to calibrate and maintain the calibration of the DDR3/2 PHY’s delay lines, provide voltage and temperature-based correction to the I/O drive impedance and ODT settings, the PHY configuration registers, testability circuitry such as the at-speed loopback controller and the DFI 2.1 interface.

A key component of the DDR3/2 PHY is the extensive in-system data training/calibration capability in order to maximize the overall timing budget and improve system reliability. The DDR3/2 PHY contains calibration circuits for read data eye training (optimizes and maintains the optimal DQS offset into the center of the read data eye), write data eye training (optimizes and maintains the optimal DQS offset into the center of the write data eye), per-bit deskew training (minimizes bit to bit timing skew for reads and writes independently), DDR3 write leveling, and DDR3 read leveling.

• When combined with a Synopsys DDR memory or protocol controller and verification IP, Synopsys provides a complete DDR3/2 interface IP solution
• Compatible with the Synopsys DDR PHY Compiler
• GUI-based tool used to assemble a customized DDR PHY targeting a specific application
• Scalable architecture that supports the speed range from DDR2-667 up to DDR3-2133
• Support for DDR3L (1.35V DDR3)
• Many DDR3/2 PHYs also support DDR3U (1.25V DDR3)
• Support for DDR2 and DDR3 DIMMs
• Delivery of product as a hardened mixed-signal macrocell component allows precise control of timing critical delay and skew paths
• Low latency
• PHY Utility Block (PUB) included as a soft IP utility that includes control features, such as write leveling and data eye training, and provides support for production testing of the DDR3/2 PHY
• DFI 2.1 interface to the memory controller
• Configurable external data bus widths between 8 and 64 bits in 8-bit increments plus ECC
• Permits operating with DDR3/2 SDRAMs using data widths narrower than the compiled data width (for example, a 32-bit interface can use just 16 bits to interface to a 16-bit wide SDRAM)
• Support for 1 to 4 memory ranks
• PHY-Controller interface runs in 1:1 or 1:2 mode (ratio of application bus clock to SDRAM clock), simplifying core logic timing constraints
• Includes the PLL and all timing circuits necessary to meet timing specifications
• Write leveling timing circuits to compensate address and control versus data delays
• Write and read bit timing circuits compensate per-bit delay skew of individual data bits within each data byte
• Locally calibrated timing circuits minimize OCV and ACLV effects, and accommodate voltage or temperature change induced timing drift
• Area optimized I/O
• 6 layers of metal
• 35um I/O pitch for 65nm
• 30um pitch for 40nm
• 25um pitch for 28nm
• Staggered I/O supported
• Supports circuit under pad (CUP) and bond overactive (BOA)
• Supports flip chip and wire bond
• I/O retention mode (available with most PHYs)
• Maintains I/O drive state during VDD power down
• Optional CKE retention mode permits VDD and all non-essential I/Os to be powered down while retaining the external SDRAMs in self refresh mode
• Accommodates any poly orientation in 28nm processes and below allowing the DDR3/2 PHY to go around a corner if required
• Advanced testability
• At-speed loopback testing on both the address and data channels
• Delay line oscillator test mode
• MUX-scan ATPG
• Optional DDR signal integrity service is available to assist customers with the integration of the PHY into their SoC, package and printed circuit board environments