Vendor: Frontgrade Gaisler Category: DDR

Fault Tolerant DDR2/DDR3/DDR4 Memory controller

FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices.

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Overview

FTADDR is a memory controller for DDR2,DDR3 and DDR4 SDRAM memory devices. It uses a strong error correction code to achieve exceptional fault tolerance.

Architecture

On the memory side, the IP presents a DFI interface for connection to an on-chip physical layer (PHY) that manages the low-level timing and data recovery and then provides the I/O buffers. Towards the system-on-chip, it presents the memory through an AMBA AHB slave interface.

Fault tolerance

  • 96-bit interface with dual x8 device correction capability
    • Ensures accurate data even in the event of one full device failure and random SEU-induced errors on other devices
  • 80-bit interface with x8 device correction capability
  • 72-bit interface with SECDEC (compatiblewith UT8SD4MQ2G72 18GB DDR4)
  • TMR and 5MR (24-bit and 40-bit) for x8 devices

Target technology support

FTADDR can be synthesized with common commercial synthesis tools. The IP model is highly configurable and portable between different implementation technologies, for both FPGA and ASIC. For FPGA, specific imlementations are available for Xilinx Ultrascale and Altera UniPhy technologies. Implementation for Microchip PolarFire is on-going.

Key features

  • DDR2, DDR3 and DDR4 support
  • Configurable to have multiple AHB ports with concurrent accesses to different memory banks
  • 96-, 80-,72-, 64-, or 32-bits interface towards SDRAM
    • Devices of width x8 or x4
  • Support for several PHYs
    • Generic DFI
    • Altera UniPhy (64 bits)
    • Xilinx Ultrascale (64 or 64+32)
    • Microchip PolarFire (implementation on-going)
  • Up to 8 parallel banks (chip selects)
  • Can operate autonomously (designed to support also processor-less configurations)
  • 96-bit interface with dual x8 device correction capability
    • Ensures accurate data even in the event of one full device failure and random SEU-induced errors on other devices
  • 80-bit interface with x8 device correction capability
  • 72-bit interface with SECDEC (compatiblewith UT8SD4MQ2G72 18GB DDR4)
  • TMR and 5MR (24-bit and 40-bit) for x8 devices
  • Planned future implementations:
    • NarrowMode (support for x8 and x16 devices)
    • Supportfor CRC on the command bits

Block Diagram

FTADDR block diagram

Specifications

Identity

Part Number
FTADDR
Vendor
Frontgrade Gaisler
Type
Silicon IP
Controller / PHY
Controller

Standards & Interfaces

Memory
DDR2 , DDR3 , DDR4

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Frontgrade Gaisler
HQ: Sweden
Contact Frontgrade Gaisler

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Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is Fault Tolerant DDR2/DDR3/DDR4 Memory controller?

Fault Tolerant DDR2/DDR3/DDR4 Memory controller is a DDR IP core from Frontgrade Gaisler listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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