How Secure DDR Interfaces Protect DRAM from Memory Attacks
Brett Murdock, Dana Neustadter (Synopsys)
Vendor:
Eureka Technology, Inc.
Category:
DDR
DDR2 SDRAM Controller
DDR2 SDRAM Controller
Key features
- Supports industry standard Double Data Rate (DDR) and Double Date Rate2 (DDR2) SDRAM from 64Mbit to 2Gbit device sizes.
- Issue precharge, active and read/write commands to a different banks and keeps multiple banks active at the same time.
- Integrated data buffer (Soft PHY) captures and synchronizes SDRAM data using programmable delay cells or DLL.
- Supports bulit-in soft DDR PHY or external hard PHY such as DFI.
- User controlled variable additive latency for DDR2 device.
- On-die termination (ODT) support optimized for single and multiple SDRAM DIMM.
- Off-Chip Driver impedance adjustment (OCD) support for DDR2 devices.
- Programmable SDRAM access timing parameters and configurations.
- Automatic refresh generation with programmable refresh intervals.
- Self-refresh mode to reduce system power consumption.
- Differentiating Features
- Multi port input.
- Mobile DDR.
- Multiple clock domain for user ports.
- Multiple SoC and FPGA standard bus interface support (e.g. AHB, Avalon, PowerPC, Wishbone, SH4).
Block Diagram
EP532 block diagram
Specifications
Identity
Part Number
EP532
Vendor
Eureka Technology, Inc.
Type
Silicon IP
Controller / PHY
Controller
Standards & Interfaces
Memory
DDR2
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about DDR Interface IP
What is DDR2 SDRAM Controller?
DDR2 SDRAM Controller is a DDR IP core from Eureka Technology, Inc. listed on Semi IP Hub.
How should engineers evaluate this DDR?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.