Vendor: Microtronix Datacom Ltd. Category: DDR

Streaming Multi-port SDRAM Memory Controller

The Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory.

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Overview

The Streaming Multi-port SDRAM Memory Controller IP Core provides a native RD or WR local port bus interface to SDRAM memory. The core integrates: a burst memory controller core, a port arbitrator, and intelligent look-ahead FIFO controller into one easy-to-use core. It supports SDR, DDR, DDR2, and Mobile DDR memory devices in a single IP Core assuring designers of a smooth low-risk migration path with changing SDRAM technology.

The core supports up to ten independently clocked streaming data sources operating from one shared high-bandwidth memory system. Using the intuitive Microtronix GUI interface, with a few clicks of a mouse, designers can create a multi-port system, a design task which would normally take several man-months of effort!

Key features

  • 200/333 MHz (400/666 Mbps) Cyclone / Stratix memory performance
  • SDR, DDR, DDR2, and Mobile DDR SDRAM memory devices
  • Up to 10 native RD or WR ports
  • Memory data width: 8/16/32/64-bit
  • Local bus width from 8 to 128-bits
  • Configurable FIFO depth: 16 to 2048 bytes
  • Intelligent SDRAM burst caching minimizes wait-states
  • Layout independent DDR/DDR2 Round-Trip capture scheme
  • Requires only single PLL with 4 clock outputs
  • Multiple time domain clocking
  • Configuration GUI streamlines design process
  • Supports Cyclone II, III, IV-E, IV-GX, Stratix II, II-GX, III, Arria GX/II-GX

Block Diagram

1588076 block diagram

Benefits

  • MegaWizzard GUI for ease of configuration
  • DQS data capture clocking simplifies MDDR/DDR/DDR2 PCB design constraints
  • Configurable FIFO optimizes streaming video applications
  • Configurable memory and local bus data width
  • Independent time domain clocking optimizes memory bandwidth
  • Synopsis TimeQuest support ensures timing closure (except for SDR memory devices Source-synchronous Data Capture)

What’s Included?

  • Easy to use configuration GUI
  • VHDL IP functional simulations models
  • On Die Termination (ODT) improves signal integrity
  • IP Core License includes 1 year of updates
  • Altera OpenCore Plus evaluation

Specifications

Identity

Part Number
1588076
Vendor
Microtronix Datacom Ltd.
Type
Silicon IP
Controller / PHY
Controller

Files

Product Sheet Download

Note: some files may require an NDA depending on provider policy.

Provider

Contact Microtronix Datacom Ltd.

Learn more about DDR IP core

Which DDR SDRAM Memory to Use and When

This whitepaper provides an overview of the JEDEC memory standards to help SoC designers select the right memory solution, including IP, that best fits their application requirements.

Frequently asked questions about DDR Interface IP

What is Streaming Multi-port SDRAM Memory Controller?

Streaming Multi-port SDRAM Memory Controller is a DDR IP core from Microtronix Datacom Ltd. listed on Semi IP Hub.

How should engineers evaluate this DDR?

Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this DDR IP.

Can this semiconductor IP be compared with similar products?

Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.

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