Low-Power Deeply Embedded RISC-V Processor

The BA53 is a configurable, low-power, deeply-embedded RISC-V processor IP core. It implements a single-issue, in-order, 5-stage execution pipeline, and supports the RISC-V 32-bit base integer instruction set (RV32I), or the 32-bit base embedded instructions set (RV32E).

Configuration Options for Broad Application Support

The processor core can be configured to meet different application requirements. It can optionally support user and supervisor privilege modes, as well as the ISA extensions for Compressed Instructions (C), Integer Multiplication and Division Instructions (M), Atomic Instructions (A), User-Level Interrupts (N), Control and Status Register (Zicsr), and Instruction-Fence (Zifencei). Support for the single-precision floating-point (F), double-precision floating-point (D). And code size reduction (Zc) ISA extensions can also be added upon request.

Furthermore, the BA53 supports software and timer interrupts and up to 64 external interrupt lines. It features a remarkably low interrupt response time, which makes the core ideal for real-time control applications. The time elapsed from when an external interrupt is asserted until the first instruction in the resolved interrupt handler can be issued is just four clock cycles.

The user can minimize the core’s silicon footprint by choosing not to implement internal modules such as the machine mode internal timers and counters; the vectored interrupt controller (VIC); or the debug, power management (PMU), or memory protection (MPU) units. Finer-grained controls give users the means to further tune the processor’s features and size to their specific design needs, including the number and size of memory regions for the MPU, the mapping of memory addresses to interfaces, and the width of the instruction and data buses.

Compact & Energy Efficient

Designed for low energy consumption, the BA53 is compact and enables advanced power management. Under its minimal configuration, the processor size is just 30k gates This small silicon footprint is critical for minimizing leakage currents during idle or standby modes and for reducing dynamic power consumption. The BA53 also enables dynamic clock gating or power shut-off of unused modules, and dynamic frequency scaling of the bus and the CPU. The carefully designed and balanced pipeline allows clocking the BA53 with clock frequencies exceeding 1GHz even on a 16nm technology.

Easy Integration and Low Risk

The processor core uses AMBA^® AXI-4 and low-latency Quick-access Memory (QMEM) interfaces for fetching instructions and accessing data and peripherals. The debug unit connects to an external JTAG/TAP controller via an APB port.

Part of the family of processor cores available from CAST for nearly ten years and used by hundreds of customers, the BA53 IP core has been designed for easy reuse and integration. It has been rigorously verified and is LINT-clean, scan-ready, and silicon-proven. It is available in Verilog source code for ASICs or FPGAs

• Efficient Deeply Embedded Processor
  • Single-issue, in-order, 5-stage pipeline 
    • 2.53 Coremarks/MHz
    • Over 1 GHz in 22 nm 
  • Small silicon footprint for lower leakage and dynamic CPU power 
    • From 30k gates 
  • Advanced power management
    • Dynamic clock gating and unused units power shut-off
    • Software- and hardware-controlled clock frequency scaling
  • Harvard architecture with separate instruction and data AXI- Lite and Quick-access Memory (QMEM) buses
• RISC-V Compatible 
  • 32-bit Base RISC-V ISA (I/E) with optional M, A, Zicsr, Zifencei, C, N, F, D, and Zc Extensions
  • Supervisor, User, and Machine Modes 
  • Memory protection unit with a configurable number of regions
  • Core Local Interrupt Controller (CLINT) for time and software interrupts
  • Programmable or Vectored Interrupt Controller (PIC or VIC) for up to 64 direct external interrupts 
• Available Pre-Integrated Platforms
  • Integrate bus fabric with peripherals such as GPIO, UART, Real-Time Clock, Timers, I2C, and SPI
  • Optionally customized to include memory controllers, interconnects, and more from the CAST IP line
• Deliverables
  • Available in Verilog source code
  • Comprehensive Documentation
  • BeyondStudio IDE for RISC-V (upon request)
  • Testbench and sample simulation scripts
• Low-Risk & Flexible Licensing
  • Reliable vendor with an extensive track record and excellent support
  • Industry-standard licensing terms with royalty-free options  
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