The VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression).
- VESA DSC
Interface and connectivity IP cores enable communication between components, chips, and systems in modern SoC and ASIC designs.
These IP cores implement a wide range of communication standards including high-speed serial interfaces, on-chip interconnects, chiplet and die-to-die links, and low-speed control interfaces.
This catalog allows you to explore and compare connectivity IP cores from leading vendors based on bandwidth, latency, protocol support, and process node compatibility.
Whether you are designing high-performance computing systems, data center processors, automotive platforms, or embedded systems, you can find the right interface IP for your communication requirements.
The VDC-M 1.2 Decoder IP Core fully complies with VESA VDC-M 1.2 (Display Compression).
32G Multi Rate SerDes PHY - GlobalFoundries 22FDX
Extoll’s SerDes architecture is based on digital design elements and methodologies.
Multi-PHY Receiver Link Controller
CD12842M8LRM3BM4AIP312P5 is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system.
MIPI D-PHY TX/CSI2 Link Controller
CD12631S4TIP is a link IP that allows you to link a camera module or CMOS image sensor (CIS) to a host system.
The Compute Express Link™ (CXL™) 2.0 Controller (formerly XpressLINK) leverages a silicon-proven PCIe 5.0 controller architecture…
SLVS-MI/MIPI-DPHY Transmitter - 4-Lane 2500Mbps
The CL12821I4T2JM2NIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
SLVS-MI Transmitter - 4-Lane 2500Mbsps
The CL12811I4T1ES1HIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
MIPI D-PHY Transmitter 4-Lane (4-Data/1-Clock) 250Mbps
The CL12631I4T1AS1BIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
MIPI M-PHY v4.1 IP, Silicon Proven in TSMC 12FFC
The MIPI M-PHY Gear 4 IP is compliant with the latest MIPI Feature Storage IP Solution SerDes PHY Product Brief Alliance M-PHY v4…
MIPI D-PHY Rx IP, Silicon Proven in UMC 55LP
The MIPI D-PHY Analog RX IP Core completely complies with the D-PHY specification, version 1.2.
We provide configurable USB 2.0 device controller IP Cores.
HDMI 2.0 Rx PHY & Controller IP, Silicon Proven in TSMC 12FFC
This HDMI 2.O Rx IP provides a HDMI receiver function and complies with HDMI specification version 2.0b.
Network Redundancy (HSR & PRP) core
The HSR&PRP Core from NetTimeLogic is a standalone Network Redundancy Core according to IEC62439-3 rev3.
Radio Clock (DCF77) Master core
NetTimeLogic’s DCF Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…
Radio Clock (DCF77) Slave core
NetTimeLogic’s DCFSlave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to a DC…
NMEA Time of Day (ToD) Slave core
NetTimeLogic’s NMEATime Of Day (ToD) Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to …
NMEA Time of Day (ToD) Master core
NetTimeLogic’s Time Of Day (ToD) Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to syn…
NetTimeLogic’s IRIG Slave Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize to an…
NetTimeLogic’s IRIG Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize othe…
Pulse Per Second Master (PPS) core
NetTimeLogic’s PPS Master Clock is a full hardware (FPGA) only implementation of a synchronization core able to synchronize other…