SLVS-MI Transmitter - 4-Lane 2500Mbsps

The CL12811I4T1ES1HIP2500 is an ideal means to link Camera Modules or CMOS Image Sensor (CIS) to Host System.
The CL12811I4T1ES1HIP2500 converts the input parallel data to the serial data and output it.
The CL12811I4T1ES1HIP2500 is designed to support maximum 2.5Gbps data rate utilizing SLVS-MI.

• SLVS-MI compliant
• Supporting for two kind Differential Output Signals: SLVS-MI (Maximum 2.5Gbps)
• Input Clock Frequency: (SLVS-MI 10bit SER) PCK_N= ~250MHz
• Power Supply : 2.8V, 1.2V(PLL/BGR) 1.2V(PHY)
• Max TX Lane Number: 4-Lane
• Data Input Path: SLVS-MI (10bit Parallel)
• Include Power Down Mode
• Include Output clock's On/Off Mode
• Include Dp, Dm polarity Control
• TPSCo 65nm BSB Process:
  • Triple well structure Layer: 7M/1L (1M~6M, 9M, L) 1.2V / 3.3V Transistor
• Various process porting support available (Please contact us.)
• Supporting Link-layer (Soft Macro): CD12811

• We are IP design professional engineering company, so we can provide the high quality and good performance solution. Also we can provide not only single-interface PHY but also multi-interface PHY.
• We are making the PHY to meet customer specification by having our own IP data base resource. Our business is very flexibility IP license model, and then we have a lot of license to many sensor companies.
• Our products can contribute to your business.

• Camera Application
• Security Camera
• Mobile-Phone Camera
• DSC(Digital Still Camera)
• Medical Camera
• SLR
• 3D Camera
• Camcorder
• ISP(Image Signal Processer)

• Verilog Model (verilog / vcs)
• .db file / .lib(Option) file
• symbol / LVS netlist / Hspice netlist(Option)
• LEF, layer map file, layout technology file
• Layout Verification Report (DRC & LVS), Command file
• Datasheet (This file) /Application Note (Usage connection CIS)
• Packaging and Layout Guideline / PCB Guideline
• Static Delay Analysis (STA) Guideline
• Testing Guideline (Option)
• TX or RX Verilog Model and Test Vector(Option)
• CMOS Image Sensor Verilog Models(Option)
• Combo Link Layer IP(CD12811IP) and FPGA Board(Option)