Audio I2S-TDM Transceiver

The I2 S/TDM Audio Transceiver is a configurable audio interface for transmitting and receiving serial audio
signals. It supports master and slave configurations, dynamic routing of multiple channels over a configurable
number of pins, and several sample sizes and frame formats. The Control and Status Registers (CSR) interface
supports the AMBA APB or AXI Lite protocols. The audio data may be input and output via the control interface,
or using the streaming data input and output. The I2 S/TDM Audio Transceiver has four clock domains: the
system clock, the audio master clock, and the receiver and transmitter bit clocks. The bit clocks are used as
true clocks and not as sampled clocks to support a high channel count. The IP is currently supported for use
in ASICs and FPGAs.

• Full-duplex operation
• Hardware configurable number of receive and transmit data pins, audio channels and TX/RX FIFO
• depths.
• High-channel count, for example, 43 channels @48KHz/24-bit/100MHz bit clock frequency
• Minimum allowed audio master clock frequency: 2× channel count × sample width
• Minimum allowed system clock frequency: audio master clock frequency / sample width (assuming 1-
• cycle FIFO read/write)
• Interrupt pins triggered when the RX FIFO reaches an upper programmable level, or the TX FIFO reaches
• a lower programmable level.
• Four clock domain design: system clock, audio master clock, TX and RX bit clocks
• Control and status registers via AMBA APB or AXI4 Lite slave interface
• Data movement using CPU or external AXI4 Stream interfaces
• Software configurable master/slave operation, used data pins, sample rate, channel size, sample size,
• data delay, fsync and bit clock frequencies and polarities, FIFO trigger levels, and channel to pin routing.

• Very high channel count (tens to hundreds).
• Software configurable I2S and TDM formats.
• Software configurable channel to the pin routing table.
• Compact hardware implementation with low power consumption.

• Audio connectivity
• Audio encoder
• Audio decoder
• Audio data converter
• Audio digital to analog conversion
• Audio analog to digital conversion

• ASIC or FPGA synthesized netlist or Verilog source code
• Verification environment with testbench
• User documentation for easy system integration
• Example integration in IOb-SoC (optional)
• ASIC or FPGA synthesis and implementation scripts or