World's First Standards-Compliant 112G PHY IP for Linear Optics: A Turning Point for AI Interconnects
Synopsys delivers standards-compliant 112G PHY IP for linear optics, helping reduce AI interconnect power, latency, and heat.
Vendor:
Synopsys, Inc.
Category:
UALink
Verification IP for UALink
Specifications: UAL_200 1.0 Interfaces: 802.3 dj compliant, UPLI DUT Types/Topology: Protocol TL Phy DL Reconciliation Sub Layer…
Overview
Specifications: UAL_200 1.0
Interfaces: 802.3 dj compliant, UPLI
DUT Types/Topology:
- Protocol
- TL
- Phy
- DL
- Reconciliation Sub Layer
- Full Stack
Debug and Analysis:
- Verdi based protocol and performance analysis
- Protocol checks at each layer
- Debug Ports
- Multiple log options
Key features
- API based transaction flow for ease of use
- Specification linked Protocol checks and functional coverage
- Exceptions, callback, error injection and analysis ports for Scoreboard
- TLM ports at each layer for traffic tracing
- Configurable timers for threshold testing
- Reference example illustrating sanity usage and representative protocol scenarios
- Can be used in Active as well as in Passive mode
Block Diagram
Verification IP for UALink block diagram
Specifications
Identity
Part Number
Verification IP for UALink
Vendor
Synopsys, Inc.
Type
Verification IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
USA
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Frequently asked questions about UALink IP cores
What is Verification IP for UALink?
Verification IP for UALink is a UALink IP core from Synopsys, Inc. listed on Semi IP Hub.
How should engineers evaluate this UALink?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this UALink IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.