PHY and SerDes IP cores are essential building blocks for high-speed data transmission in modern semiconductor designs. This category includes physical layer IP and serializer/deserializer solutions used to implement reliable chip-to-chip, die-to-die, backplane and interface connectivity across networking, compute, storage, automotive and consumer applications.
Browse PHY / SerDes semiconductor IP for high-speed interfaces requiring robust signal integrity, scalable lane configurations, low power and standards-oriented interoperability. Compare controller-adjacent PHY IP, generic SerDes architectures and specialized high-speed connectivity solutions from multiple vendors for integration into ASICs, SoCs and advanced package designs.
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI CDPHY Master V2.1/V3.0
This is a DPHY IP compliant to the “MIPI Alliance Spec for C-PHY v2.1 and D-PHY v3.0”, which consists of Bi-directional 1-Clock a…
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Slave V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
GLOBALFOUNDRIES 22nm FDX MIPI DPHY Master V1.2
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of 1-Clock and 4-Data lanes.
This is a DPHY IP compliant to the “MIPI Alliance Spec for D-PHY v1.2”, which consists of Bi-directional 1-Clock and 4-Data lanes.
MIPI C-PHY v2.0 /D-PHY v2.5 Combo IP in TSMC
MIPI D-PHY is a serial interface technology which is widely adopted in smartphones and other multimedia enabled mobile devices.
Dolphin Technology provides JTAG Controller (TAP) IP which enables access through the JTAG interface for building designs with ef…
The Actt's 16G SerDes IP is a high performance Multi-lane SerDes PHY IP designed for chips that perform high bandwidth data commu…
The Actt's 6.25G SerDes IP is a 4-Channel Serdes configuration with 1 PLL, 4 TX channels and 4 RX channels.
The ACTT family of interface IP for MIPI protocols is the way with mobile-optimized low power and high performance.
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…
Gigabit Ethernet PHY
10/100/1000 base T ethernet Phy
IP
PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
M31 PCIe 5.0 PHY IP provides high-performance, multi-lane capability and low power architecture for high-bandwidth applications.
USB4 Gen3X2 and DP1.4 X4 PHY IP with Type-C connector support
M31 USB4 Gen3x2 transceiver IP provides a range of USB4 Gen3x2 host and peripheral applications up to 40Gbps.
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
The multi-channel, multi-speed Ethernet universal media access control (MAC) and physical coding sublayer IP (UMAC) is fully conf…
Gigabit Ethernet PHY