What is GLink Multi-Slice PCS?
GLink Multi-Slice PCS is a Single-Protocol PHY IP core from Global UniChip Corp. (GUC) listed on Semi IP Hub.
Vendor:
Global UniChip Corp. (GUC)
Category:
Single-Protocol PHY
GLink Multi-Slice PCS
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…
Overview
GLink Multi-Slice PCS (IGDD2D004A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure consistent data arriving at the RX side in spite of different delays of TX and RX PCS FIFOs of different slices.
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
GLink Multi-Slice PCS is a configurable design for a specific multi-slice configuration. By specifying number of user interface and the corresponding data bus width, and whether different user interface would be merged into one GLink Slice, a specific GLink Multi-Slice PCS design could be provided, including RTL code with timing constraints and a testbench.
The Multi-Slice PCS is compatible with any revision of GLink IP, and it provides the error indication in case of alignment fail.
Key features
- Align data buses of different GLink Slices
- Compatible with any revision of GLink IP
- VALID and READY handshake mechanism
- Support any data bus width
- Support multiple data buses merge to same GLink Slice
- Support at most eight combined Slices
- TX Multi-Slice PCS latency is 0 TX clock
- RX Multi-Slice PCS latency is default 1 RX clock
- Provide alignment fail status
Specifications
Identity
Part Number
IGDD2D004A
Vendor
Global UniChip Corp. (GUC)
Type
Silicon IP
Files
Note: some files may require an NDA depending on provider policy.
Provider
HQ:
Taiwan
Frequently asked questions about Single-Protocol PHY IP
How should engineers evaluate this Single-Protocol PHY?
Engineers should review the overview, key features, supported foundries and nodes, maturity, deliverables, and provider information before shortlisting this Single-Protocol PHY IP.
Can this semiconductor IP be compared with similar products?
Yes. Buyers can compare this product with similar semiconductor IP cores or IP families based on category, provider, process options, and structured technical specifications.