10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
- Single-Protocol PHY
- Silicon Proven
- Q2, 2024
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
10Base-T/100Base-TX Fast Ethernet PHY
Gigabit Ethernet PHY
PCIe Gen4 RX/TX IP Supporingt PCIe 1.0/2.0/3.0/4.0 up to 16Gbps. CTLE boosts up to 18dB at 8GHz
Support PCIe 1.0/2.0/3.0/4.0 up to 16Gbps.
The HDMI Rx PHY is the physical layer of an HDMI receiver.
PHY layer solution for PCIe1.1/PCIe2.0 with a serial interface and PIPE3 compliant digital interface
KA13UGPEP20ST001 provides a PHY layer solution for PCIe1.1/PCIe2.0 (2.5/5.0Gbps) for single lane application.
PCIe 6.0 PHY G2 , SS SF4X x4, North/South (vertical) poly orientation
The multi-channel Synopsys PHY IP for PCI Express® (PCIe®) 6.0 meets today’s demands for higher bandwidth and power efficiency ac…
USB-C 3.2 DP/TX PHY ebdaux in Samsung (SF4X, SF4E, SF2)
The Synopsys USB-C 3.2/DisplayPort 1.4 IP solution consists of USB-C 3.2/DisplayPort 1.4 PHYs, USB-C 3.2/DisplayPort 1.4 controll…
The HDMI Tx PHY is the physical layer of a single-link HDMI transmitter interface.
The HDMI Rx PHY is the physical layer of an HDMI receiver.
The XAUI PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into XAUI …
The SATA 6G PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into SA…
The PCIe2 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into PCI …
The PCIe1 PHY is a mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into comp…
The USB 3.0 PHY is a , mixed-signal semiconductor intellectual property (IP) solution, designed for single-chip integration into …
The USB 2.0 PHY is a mixed-signal IP solution designed to implement OTG connectivity in a System-on-Chip (SoC) design targeted to…
Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
The USB3.0 Super-Speed / PCI Express Combo PHY is a programmable IP that is compatible with the PHY Interface for PCI Express and…
SMIC 0.11um USB2.0 Dual Role PHY
The USB 2.0 dual role PHY is a Hi-Speed USB peripheral transceiver IP that implements the Intel® UTMI standard.
GLink Multi-Slice PCS (IGPD2D001A) is a digital IP used to provide data bus alignment between different GLink Slices to ensure co…