The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
- PCIe Gen4
Single-Protocol PHY IP cores help engineering teams evaluate reusable semiconductor IP for advanced chip designs.
This page lets you compare Single-Protocol PHY IP offerings from multiple vendors based on functionality, integration requirements, performance targets, power efficiency, and process compatibility.
The TRC5024CPA is a four lane Gen 1 and 2 PCI Express Physical layer (Phy) Phy IP core, delivering high-speed serial data transmi…
USB 1.1 PHY in TSMC(40nm, 55nm, 90nm ULP process )
M31 provides customers with a unique USB 1.1 PHY IP for IoT applications.
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USB2.0 PHY - SMIC 110nm generic
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USB 2.0 PHY - SMIC 55nm Eflash
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USB 2.0 PHY - SMIC 55nm Eflash
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LVDS transmitter - TowerJazz 0.13um
LVDS transmitter
LVDS receiver - TowerJazz 0.13um
LVDS receiver
LVDS reference - TowerJazz 0.13um
LVDS reference
USB 2.0 PHY in TSMC(6nm, 7nm, 12nm, 16nm, 22nm, 28nm, 40nm, 55nm, 65nm, 90nm)
M31 provides customers the next generation of USB 2.0 IP with an extremely compact die area and lower active and suspend power co…
USB 3.2 Gen2/Gen1 PHY IP in TSMC(5nm,6nm, 7nm,12nm/16nm, 22nm, 28nm, 40nm, 55nm)
M31 USB 3.2 Gen2 (support x1/x2) transceiver IP provides a range of USB 3.2 Gen2 host and peripheral applications up to 10x2Gbps.
The LVDS_RX is CMOS differential line receivers designed for applications requiring ultra low power dissipation, low noise, and h…
The LVDS_TX is CMOS differential line transmitter designed for applications requiring ultra low power dissipation, low noise, and…
10Base-T Interface - requires no PHY
Full support for 10Base-T, full- or half-duplex