Overview
The Synopsys USB 2.0 picoPHY provides designers with a complete physical (PHY) layer IP solution, designed for low power mobile and consumer applications such as next—generation, feature-rich smartphones, netbooks, and mobile internet devices. For reduced silicon cost and longer battery life, the Synopsys USB 2.0 picoPHY IP delivers smaller die area and lower leakage power compared to current USB 2.0 PHY IP products. Optimized for mobile and consumer electronic applications, the Synopsys USB 2.0 picoPHY implements the latest Battery Charger version 1.1 and USB On-The-Go (OTG) version 2.0 specifications from the USB Implementer’s Forum (USB-IF). Architected for the industry’s most advanced process technologies, the USB 2.0 picoPHY is designed with features created to minimize effects due to variations in foundry process, device models, package and board parasitics. The Synopsys USB 2.0 picoPHY builds on years of customer success with Synopsys’ silicon-proven USB 2.0 PHY IP product line, which has been ported to over 50 process node and configuration combinations ranging from 180nm to 28nm. When combined with the Synopsys Host, Device or On-The-Go (OTG) digital controllers and verification IP, the Synopsys USB 2.0 picoPHY delivers a complete low power and small die area solution for advanced system-on-chip (SoC) designs.
Learn more about Single-Protocol PHY IP core
Model authoring kits (MAKs) enable the rapid development of transaction-level models, TLMs, of a given functionality or protocol. MAKs include base functionalities that are common to all models independent of the RTL implementation in a well-structured way, allowing for maximum reuse. The DesignWare System-Level Library provides MAKs for UART and USB. Taking the example of a USB 2.0 EHCI controller model using MAKs, this paper explains the significant design time reduction that can be achieved.
This article discusses the road to achieving compliance and the role that Synopsys DesignWare Intellectual Property (IP) for PCI Express can play in helping to achieve interoperability and compliance
Using complete, integrated DDR2 SDRAM memory physical interface IP solutions can significantly reduce the risks associated with combining discrete memory subsystem blocks, such as interoperability and schedule. Packaged as a complete, integrated place-and
Discover Synopsys’ first complete UFS 5.0 and M‑PHY v6.0 IP solution for high-speed, efficient storage in mobile, automotive, and AI-enabled systems.
Synopsys continues to lead innovation with the industry’s first commercially available CXL 4.0 Verification IP (VIP). This comprehensive solution supports the full 128 GT/s data rate, IO throttling, and streamlined port negotiation, equipping designers to validate and optimize their products for the future.
In our current work, we focus on the low power analysis and verification challenges and the methodology used to verify low power design. The power-gating feature that we term Hibernation brings in significant power savings to Synopsys SSIC IP Controller. The verification tests the functionality of the Controller before, during and after hibernation state. The low power analysis will showcase the power savings achieved in SSIC IP with and Without Hibernation.
